Quoting Tvrtko Ursulin (2017-07-24 09:06:28) > > > On 21/07/2017 17:11, Chris Wilson wrote: > > We require the caller to ensure that the packets they wish to emit into > > the CS ring are qword aligned (i.e. have an even number of dwords). > > Double check this. > > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx> > > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index aa59290cb8bf..0b06f66507a0 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -1397,6 +1397,9 @@ u32 *intel_ring_begin(struct drm_i915_gem_request *req, > > unsigned int total_bytes; > > u32 *cs; > > > > + /* Packets must be qword aligned. */ > > + GEM_BUG_ON(num_dwords & 1); > > + > > total_bytes = bytes + req->reserved_space; > > GEM_BUG_ON(total_bytes > ring->effective_size); > > > > > > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx> And pushed! Still looking for takers to review a regression fix or two... :-p -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
