Hi Andrzej,
Thanks for the feedback. Can you tell me if that following changes are
correct?
Cheers,
-
Lionel
On 25/07/17 10:06, Datczuk, Andrzej wrote:
Hi Lionel,
What about the corrected whitelist I sent you before? Without allowing those registers the patch for MDAPI is basically useless.
FYI The whitelist from the patches I sent you contained merged ranges for gen7-9 platforms.
Regards,
Andrzej
+static bool gen8_is_valid_flex_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+ static const i915_reg_t flex_eu_regs[] = {
+ EU_PERF_CNTL0,
+ EU_PERF_CNTL1,
+ EU_PERF_CNTL2,
+ EU_PERF_CNTL3,
+ EU_PERF_CNTL4,
+ EU_PERF_CNTL5,
+ EU_PERF_CNTL6,
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
+ if (flex_eu_regs[i].reg == addr)
+ return true;
+ }
+ return false;
+}
+
+static bool gen7_is_valid_b_counter_addr(struct drm_i915_private
+*dev_priv, u32 addr) {
+ return (addr >= 0x2380 && addr <= 0x27ac); }
Here I dropped 0x2b20 because it's an interruption register. It probably
should be left to its default value and only managed by the kernel.
Though I made a mistake as this should be addr >= 0x2374 && addr <= 0x27ac.
+
+static bool gen7_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+ return addr == NOA_WRITE.reg ||
+ (addr >= 0xd0c && addr <= 0xd3c) ||
Arg, missing 0xd24/0xd28 here...
+ (addr >= 0x25100 && addr <= 0x2FB9C); }
+
+static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+ return (addr >= 0x25100 && addr <= 0x2FF90) ||
+ gen7_is_valid_mux_addr(dev_priv, addr); }
+
+static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv,
+u32 addr) {
+ return (addr >= 0x182300 && addr <= 0x1823A4) ||
+ gen7_is_valid_mux_addr(dev_priv, addr); }
+
+
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