Quoting Chris Wilson (2017-07-21 17:11:01) > We require the caller to ensure that the packets they wish to emit into > the CS ring are qword aligned (i.e. have an even number of dwords). > Double check this. > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx> > Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index aa59290cb8bf..0b06f66507a0 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1397,6 +1397,9 @@ u32 *intel_ring_begin(struct drm_i915_gem_request *req, > unsigned int total_bytes; > u32 *cs; > > + /* Packets must be qword aligned. */ > + GEM_BUG_ON(num_dwords & 1); GEM_BUG_ON(!IS_ALIGNED(num_dwords, 2)) ? GEM_BUG_ON(!IS_ALIGNED(num_words, DWORDS_PER_QWORD)) ? -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
