On Tue, Jul 11, 2017 at 11:42:35PM +0300, Imre Deak wrote: > The pattern of a power well backing a set of fuses whose initialization > we need to wait for during power well enabling is common to all GEN9+ > platforms. Adding support for this to the HSW power well enable helper > allows us to use the HSW/BDW power well code for GEN9+ as well in a > follow-up patch. > > v2: > - Use an enum for power gates instead of raw numbers. (Ville) Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@xxxxxxxxx> _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
