On Thu, Jul 20, 2017 at 07:57:54PM +0200, Daniel Vetter wrote:
> The core already does this in setup_commit(). With this we can also
> remove the unpin_work_count since it's the last user, and also remove
> the loop since that was only used for stalling against legacy flips.
>
> v2: Amend commit message a bit (Chris).
>
> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
Ok, I pulled in 4-7 of this series. I'll drop 2&3 since they're not a
complete solution.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 +------------
> drivers/gpu/drm/i915/intel_drv.h | 2 --
> 2 files changed, 1 insertion(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c10966ebf6fc..1009ad9d8221 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11830,18 +11830,7 @@ static int intel_atomic_check(struct drm_device *dev,
> static int intel_atomic_prepare_commit(struct drm_device *dev,
> struct drm_atomic_state *state)
> {
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct drm_crtc_state *crtc_state;
> - struct drm_crtc *crtc;
> - int i, ret;
> -
> - for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
> - if (state->legacy_cursor_update)
> - continue;
> -
> - if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
> - flush_workqueue(dev_priv->wq);
> - }
> + int ret;
>
> ret = mutex_lock_interruptible(&dev->struct_mutex);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 9cb7e781e863..96402c06e295 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -798,8 +798,6 @@ struct intel_crtc {
> unsigned long long enabled_power_domains;
> struct intel_overlay *overlay;
>
> - atomic_t unpin_work_count;
> -
> /* Display surface base address adjustement for pageflips. Note that on
> * gen4+ this only adjusts up to a tile, offsets within a tile are
> * handled in the hw itself (with the TILEOFF register). */
> --
> 2.13.2
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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