These patches, along with an upcoming series for IGT, enable our PSR IGT tests to run reliably once again on HSW, BDW, and SKL. The first change enables us to run the PSR tests on some RVP platforms whose panels have too slow of a setup time when running in their preferred mode. The second fixes a minor problem with the way that we were initializing SRD_CTL that caused us to clobber a bit that we are not supposed to change in that register on SKL and KBL. The third change re-introduces some changes to our link training code to be less aggressive about changing link state for eDP, because PSR depends on the link state being the same at PSR exit as it was at PSR entry. The fourth change greatly increases the reliability of reading the sink CRC generated by the eDP panel. v2 Highlights: * Rebased to current drm-tip * Greatly reduced looping around trying to read sink CRC (Jani) * Reduce amount of changes in the sink CRC patch (Jani) * Field-wise init of EDP_PSR_MAX_SLEEP_TIME (Rodrigo) * Minor commit message / cover letter tweaks v3: * Re-ordered patches to put reviewed patches first. * Rebased to current drm-tip Jim Bride (4): drm/i915/psr: Clean-up intel_enable_source_psr1() drm/i915/psr: Account for sink CRC raciness on some panels drm/i915/edp: Allow alternate fixed mode for eDP if available. drm/i915/edp: Be less aggressive about changing link config on eDP drivers/gpu/drm/i915/i915_reg.h | 4 ++ drivers/gpu/drm/i915/intel_dp.c | 78 +++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_dp_link_training.c | 11 +++- drivers/gpu/drm/i915/intel_drv.h | 4 ++ drivers/gpu/drm/i915/intel_dsi.c | 2 +- drivers/gpu/drm/i915/intel_dvo.c | 2 +- drivers/gpu/drm/i915/intel_lvds.c | 3 +- drivers/gpu/drm/i915/intel_panel.c | 2 + drivers/gpu/drm/i915/intel_psr.c | 21 +++++++- 9 files changed, 111 insertions(+), 16 deletions(-) -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
