On 23/06/17 16:35, Chris Wilson wrote:
Quoting Michel Thierry (2017-06-24 00:17:29)Until Haswell/Baytrail, the hardware used to have a per engine fault register (e.g. 0x4094 - render fault register, 0x4194 - media fault register, etc). But since Broadwell, all these registers were combined into a singe one, which specifies the engine id in bits 14:12. Luckily, the additional register addresses haven't been reused, but we should not been reading (and writing to) registers that do not exist. References: IHD-OS-BDW-Vol 2c-11.15, page 75. Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 29 ++++++++++++++++++++++++----- drivers/gpu/drm/i915/i915_gpu_error.c | 8 +++++--- drivers/gpu/drm/i915/i915_reg.h | 2 ++ 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index de67084d5fcf..83deb004368c 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2000,22 +2000,41 @@ void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) if (INTEL_INFO(dev_priv)->gen < 6) return; - for_each_engine(engine, dev_priv, id) { + /* From GEN8 onwards we only have one 'All Engine Fault Register' */ + if (INTEL_INFO(dev_priv)->gen >= 8) {INTEL_GEN() >= 8
Oops, busted copy-pasting old code, I'll also change it (INTEL_INFO(dev_priv)->gen < 6).
u32 fault_reg;Newline after variable blocks (might as well fix up the coding style in passing). u32 fault; foo_reg is more commonly used to refer to the register offset itself, i.e. i915_reg_t. Might as well move it to the start of the function as it is shared between all branches, and I don't think we are overly concerned with aiding gcc's liverange analysis here.
I thought about moving it to the start of the function. Let me make these changes.
Thanks, -Michel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
