On Thu, Jun 22, 2017 at 09:43:00AM -0700, Manasi Navare wrote:
> When we read the VBT t11_t12 value for panel power cycle delay,
> it is a zero based value so we need to 100ms to that. And then it
> needs to be multiplied by 10 to store it in 100usecs unit same as
> SW VBT.
>
> v2:
> * Change the VBT value instead of HW readout and pp div (Ville Syrjala)
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index bca4ac1..be9e17a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5234,6 +5234,11 @@ intel_dp_init_panel_power_sequencer(struct drm_device *dev,
> intel_pps_dump_state("cur", &cur);
>
> vbt = dev_priv->vbt.edp.pps;
> + /* T11_T12 delay is special and actually in units of 100ms, but zero
> + * based in the hw (so we need to add 100 ms). But the sw vbt
> + * table multiplies it with 1000 to make it in units of 100usec,
> + * too. */
> + vbt.t11_t12 += 100 * 10;
If we ever encounter a two eDP panel system this would end up bumping
the delay twice for one of the panels. But if those panels wouldn't have
identical timings we'd anyway make a mess of things. Not sure how the
VBT would even present two different panels to us. So doing this here
seems OK to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
> * our hw here, which are all in 100usec. */
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
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