>-----Original Message----- >From: Intel-gfx [mailto:intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of >Clint Taylor >Sent: Wednesday, June 21, 2017 12:48 PM >To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx >Subject: Re: [i-g-t 3/3] lib/cfl: Add PCI Ids for U SKU in CFl > > > >On 06/21/2017 09:34 AM, Anusha Srivatsa wrote: >> From: anushasr <anusha.srivatsa@xxxxxxxxx> >> >> Follow the spec and add ID for U SKU >> >> v2: Update IDs. >> >> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> >> --- >> lib/i915_pciids.h | 9 ++++++++- >> 1 file changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h index >> c319e37..71cce60 100644 >> --- a/lib/i915_pciids.h >> +++ b/lib/i915_pciids.h >> @@ -346,8 +346,15 @@ >> INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ >> INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ >> >> +#define INTEL_CFL_U_IDS(info) \ >> + INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \ >> + INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ >> + INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ >> + INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ >0x3EA8 is marked as not POR in the current documentation. Wanted to match the IDs everywhere. The above list of IDs is the same even in kernel code and in libdrm . Anusha >-Clint > > >> + >> #define INTEL_CFL_IDS(info) \ >> INTEL_CFL_S_IDS(info), \ >> - INTEL_CFL_H_IDS(info) >> + INTEL_CFL_H_IDS(info), \ >> + INTEL_CFL_U_IDS(info) >> >> #endif /* _I915_PCIIDS_H */ > >_______________________________________________ >Intel-gfx mailing list >Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
