[PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write

[Manasi Navare <manasi.d.navare@xxxxxxxxx>]

According to the eDP spec the minimum value for panel power cycle delay
(t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle
delay field should be programmed to "+1" value. Eg: To have a delay
of 500ms this should be programmed to 6. This patch fixes the write
by adding +1 to the pp_div value so it programs the correct min
required panel power cycle delay.
Since we program it to +1 value, when we perform HW readout, this
value should subtract 1 before verifying pps state. This patch makes
this correction as well to avoid "PPS state mismatch" error.
This patch also adds a case where if the readout is 0 for the first readout,
then read it as 0, dont subtract.

Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: Clint Taylor <Clinton.A.Taylor@xxxxxxxxx>
---
 drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bca4ac1..089e373 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
 			   struct intel_dp *intel_dp, struct edp_power_seq *seq)
 {
 	u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
+	u16 pp_cycle_delay = 0;
 	struct pps_registers regs;
 
 	intel_pps_get_registers(dev_priv, intel_dp, &regs);
@@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
 	seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
 		   PANEL_POWER_DOWN_DELAY_SHIFT;
 
-	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
-		u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
+	if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
+		pp_cycle_delay =  (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
 			BXT_POWER_CYCLE_DELAY_SHIFT;
-		if (tmp > 0)
-			seq->t11_t12 = (tmp - 1) * 1000;
-		else
-			seq->t11_t12 = 0;
-	} else {
-		seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
-		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
-	}
+	else
+		pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
+			PANEL_POWER_CYCLE_DELAY_SHIFT;
+	if (pp_cycle_delay > 0)
+		seq->t11_t12 = (pp_cycle_delay - 1) * 1000;
+	else
+		seq->t11_t12 = 0;
 }
 
 static void
@@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 				<< BXT_POWER_CYCLE_DELAY_SHIFT);
 	} else {
 		pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
-		pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
+		pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000)
 				<< PANEL_POWER_CYCLE_DELAY_SHIFT);
 	}
 
-- 
2.1.4

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