On to, 2017-04-06 at 12:15 -0700, Rodrigo Vivi wrote:
> By spec there is no change on force wake registers
> for Cannonlake. Let's reuse gen9 one.
>
> v2: Adding missing case for the write part. (Tvrtko)
> v3: Rebase on recent tree.
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Bspec: 18331
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -642,7 +642,8 @@ static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
> { .start = (s), .end = (e), .domains = (d) }
>
> #define HAS_FWTABLE(dev_priv) \
> - (IS_GEN9(dev_priv) || \
> + (IS_GEN10(dev_priv) || \
May I suggest INTEL_GEN(dev_priv) >= 9 ?
> + IS_GEN9(dev_priv) || \
> IS_CHERRYVIEW(dev_priv) || \
> IS_VALLEYVIEW(dev_priv))
>
> @@ -1177,7 +1178,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
> dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
> }
>
> - if (IS_GEN9(dev_priv)) {
> + if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {
Ditto. With those, this is:
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Regards, Joonas
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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