Re: [PATCH 5/5] drm/i915/cfl: Introduce Coffee Lake workardounds.

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On Tue, 2017-06-06 at 12:20 -0700, Rodrigo Vivi wrote:
> Coffee Lake inherit most of Kabylake production
> workardounds.
> 
> Only difference identified so far is:
> - WaDisableLSQCROPERFforOCL is marked as SIWA_NEVER
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c    |  2 +-
>  drivers/gpu/drm/i915/intel_engine_cs.c | 75 +++++++++++++++++++++++++---------
>  drivers/gpu/drm/i915/intel_pm.c        | 10 ++---
>  3 files changed, 61 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4ff854e..8e055b1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1884,7 +1884,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
>  	 * called on driver load and after a GPU reset, so you can place
>  	 * workarounds here even if they get overwritten by GPU reset.
>  	 */
> -	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk */
> +	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
>  	if (IS_BROADWELL(dev_priv))
>  		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
>  	else if (IS_CHERRYVIEW(dev_priv))
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index bc38bd1..630ff6e 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -814,24 +814,24 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	struct drm_i915_private *dev_priv = engine->i915;
>  	int ret;
>  
> -	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk */
> +	/* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
>  
> -	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk */
> +	/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
>  		   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
>  
> -	/* WaDisableKillLogic:bxt,skl,kbl */
> +	/* WaDisableKillLogic:bxt,skl,kbl,cfl */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>  		   ECOCHK_DIS_TLB);
>  
> -	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk */
> -	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk */
> +	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
> +	/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  			  FLOW_CONTROL_ENABLE |
>  			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>  
> -	/* Syncing dependencies between camera and graphics:skl,bxt,kbl */
> +	/* Syncing dependencies between camera and graphics:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>  			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>  
> @@ -851,18 +851,18 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  		 */
>  	}
>  
> -	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk */
> -	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
> +	/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
> +	/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
>  			  GEN9_ENABLE_YV12_BUGFIX |
>  			  GEN9_ENABLE_GPGPU_PREEMPTION);
>  
> -	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk */
> -	/* WaDisablePartialResolveInVc:skl,bxt,kbl */
> +	/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
> +	/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
>  					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
>  
> -	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk */
> +	/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
>  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
>  			  GEN9_CCS_TLB_PREFETCH_ENABLE);
>  
> @@ -871,7 +871,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  		WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
>  				  PIXEL_MASK_CAMMING_DISABLE);
>  
> -	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
> +	/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
>  			  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
> @@ -889,39 +889,40 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	 * a TLB invalidation occurs during a PSD flush.
>  	 */
>  
> -	/* WaForceEnableNonCoherent:skl,bxt,kbl */
> +	/* WaForceEnableNonCoherent:skl,bxt,kbl,cfl */
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0,
>  			  HDC_FORCE_NON_COHERENT);
>  
> -	/* WaDisableHDCInvalidation:skl,bxt,kbl */
> +	/* WaDisableHDCInvalidation:skl,bxt,kbl,cfl */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>  		   BDW_DISABLE_HDC_INVALIDATION);
>  
> -	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
> +	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
>  	if (IS_SKYLAKE(dev_priv) ||
>  	    IS_KABYLAKE(dev_priv) ||
> +	    IS_COFFEELAKE(dev_priv)||

GEN9_BC?


>  	    IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
>  		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>  				  GEN8_SAMPLER_POWER_BYPASS_DIS);
>  
> -	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk */
> +	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>  
> -	/* WaOCLCoherentLineFlush:skl,bxt,kbl */
> +	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
>  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>  				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>  
> -	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk */
> +	/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
>  	ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
>  	if (ret)
>  		return ret;
>  
> -	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
> +	/* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl,cfl */
>  	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
>  	if (ret)
>  		return ret;
>  
> -	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk */
> +	/* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl,glk,cfl */
>  	ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
>  	if (ret)
>  		return ret;
> @@ -1140,6 +1141,38 @@ static int glk_init_workarounds(struct intel_engine_cs *engine)
>  	return 0;
>  }
>  
> +static int cfl_init_workarounds(struct intel_engine_cs *engine)
> +{
> +	struct drm_i915_private *dev_priv = engine->i915;
> +	int ret;
> +
> +	ret = gen9_init_workarounds(engine);
> +	if (ret)
> +		return ret;
> +
> +	/* WaEnableGapsTsvCreditFix:cfl */
> +	I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
> +				   GEN9_GAPS_TSV_CREDIT_DISABLE));
> +
> +	/* WaToEnableHwFixForPushConstHWBug:cfl */
> +	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
> +			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> +
> +	/* WaDisableGafsUnitClkGating:cfl */
> +	WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
> +
> +	/* WaDisableSbeCacheDispatchPortSharing:cfl */
> +	WA_SET_BIT_MASKED(
> +		GEN7_HALF_SLICE_CHICKEN1,
> +		GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> +
> +	/* WaInPlaceDecompressionHang:cfl */
> +	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
> +		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> +
> +	return 0;
> +}
> +
>  int init_workarounds_ring(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *dev_priv = engine->i915;
> @@ -1162,6 +1195,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
>  		err = kbl_init_workarounds(engine);
>  	else if (IS_GEMINILAKE(dev_priv))
>  		err =  glk_init_workarounds(engine);
> +	else if (IS_COFFEELAKE(dev_priv))
> +		err = cfl_init_workarounds(engine);
>  	else
>  		err = 0;
>  	if (err)

Noting a couple of things that will change in the next version.
1) Commit message and title change to clarify these are GT workarounds.
2) The hunk below moves to patch 4/5. 


I am unable review the workarounds themselves, will leave it for someone
who is competent in this area to do it.


> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 98aeba9..0aed13d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -58,24 +58,24 @@
>  
>  static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
> +	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
>  	I915_WRITE(CHICKEN_PAR1_1,
>  		   I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>  
>  	I915_WRITE(GEN8_CONFIG0,
>  		   I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
>  
> -	/* WaEnableChickenDCPR:skl,bxt,kbl,glk */
> +	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(GEN8_CHICKEN_DCPR_1,
>  		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>  
> -	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
> -	/* WaFbcWakeMemOn:skl,bxt,kbl,glk */
> +	/* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
> +	/* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
>  	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
>  		   DISP_FBC_WM_DIS |
>  		   DISP_FBC_MEMORY_WAKE);
>  
> -	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
> +	/* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
>  	I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>  		   ILK_DPFC_DISABLE_DUMMY0);
>  }

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