On Tue, Jun 6, 2017 at 2:48 PM, Pandiyan, Dhinakaran <dhinakaran.pandiyan@xxxxxxxxx> wrote: > On Tue, 2017-06-06 at 11:12 -0700, Rodrigo Vivi wrote: >> On Tue, Jun 6, 2017 at 11:09 AM, Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> wrote: >> > On Tue, Jun 6, 2017 at 10:39 AM, Pandiyan, Dhinakaran >> > <dhinakaran.pandiyan@xxxxxxxxx> wrote: >> >> On Tue, 2017-06-06 at 08:24 -0700, Rodrigo Vivi wrote: >> >>> On Mon, Jun 5, 2017 at 10:04 AM, Pandiyan, Dhinakaran >> >>> <dhinakaran.pandiyan@xxxxxxxxx> wrote: >> >>> > On Mon, 2017-06-05 at 19:55 +0300, Ville Syrjälä wrote: >> >>> >> On Mon, Jun 05, 2017 at 04:41:07PM +0000, Vivi, Rodrigo wrote: >> >>> >> > On Mon, 2017-06-05 at 18:22 +0300, Imre Deak wrote: >> >>> >> > > On Thu, Apr 06, 2017 at 12:15:27PM -0700, Rodrigo Vivi wrote: >> >>> >> > > > All the low level cdclk bits are present, so let's add the required >> >>> >> > > > hooks to reconfigure cdclk on the fly. >> >>> >> > > > >> >>> >> > > > v2: Rebase due to cnl_sanitize_cdclk() >> >>> >> > > > v3: Rebased by Rodrigo on top of Ville's cdclk rework. >> >>> >> > > > v4: Rebase moving cnl_calc_cdclk up to follow same order >> >>> >> > > > as previous platforms. >> >>> >> > > > >> >>> >> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> >>> >> > > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> >> >>> >> > > > --- >> >>> >> > > > drivers/gpu/drm/i915/intel_cdclk.c | 54 ++++++++++++++++++++++++++++++++++++-- >> >>> >> > > > 1 file changed, 52 insertions(+), 2 deletions(-) >> >>> >> > > > >> >>> >> > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c >> >>> >> > > > index f9ba1e7..a8c254b 100644 >> >>> >> > > > --- a/drivers/gpu/drm/i915/intel_cdclk.c >> >>> >> > > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c >> >>> >> > > > @@ -1400,6 +1400,16 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) >> >>> >> > > > bxt_set_cdclk(dev_priv, &cdclk_state); >> >>> >> > > > } >> >>> >> > > > >> >>> >> > > > +static int cnl_calc_cdclk(int max_pixclk) >> >>> >> > > > +{ >> >>> >> > > > + if (max_pixclk > 336000) >> >>> >> > > > + return 528000; >> >>> >> > > > + else if (max_pixclk > 168000) >> >>> >> > > > + return 336000; >> >>> >> > > > + else >> >>> >> > > > + return 168000; >> >>> >> > > > +} >> >>> >> > > > + >> >>> >> > > > static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv, >> >>> >> > > > struct intel_cdclk_state *cdclk_state) >> >>> >> > > > { >> >>> >> > > > @@ -1640,7 +1650,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv) >> >>> >> > > > >> >>> >> > > > cdclk_state = dev_priv->cdclk.hw; >> >>> >> > > > >> >>> >> > > > - cdclk_state.cdclk = 168000; >> >>> >> > > > + cdclk_state.cdclk = cnl_calc_cdclk(0); >> >>> >> > > > cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); >> >>> >> > > > >> >>> >> > > > cnl_set_cdclk(dev_priv, &cdclk_state); >> >>> >> > > > @@ -1928,6 +1938,40 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) >> >>> >> > > > return 0; >> >>> >> > > > } >> >>> >> > > > >> >>> >> > > > +static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state) >> >>> >> > > > +{ >> >>> >> > > > + struct drm_i915_private *dev_priv = to_i915(state->dev); >> >>> >> > > > + struct intel_atomic_state *intel_state = >> >>> >> > > > + to_intel_atomic_state(state); >> >>> >> > > > + int max_pixclk = intel_max_pixel_rate(state); >> >>> >> > > > + int cdclk, vco; >> >>> >> > > > + >> >>> >> > > > + cdclk = cnl_calc_cdclk(max_pixclk); >> >>> >> > > > + vco = cnl_cdclk_pll_vco(dev_priv, cdclk); >> >>> >> > > >> >>> >> > > The spec says not to set CDCLK to 168MHz if audio is used with 96MHz >> >>> >> > > BCLK, what's the plan to add that constraint? At least there could be a >> >>> >> > > TODO: here. >> >>> >> > >> >>> >> > That's a good question. >> >>> >> > Do we have ways to know the audio freq? >> >>> >> > Or we need to add few extra hooks? >> >>> >> > And agree, at least a TODO or FIXME here is needed while we dont have a >> >>> >> > clear path. >> >>> >> >> >>> >> bdw_adjust_min_pipe_pixel_rate() just assumes 96MHz. There was some >> >>> >> discussion on the topic, and I found some register that possibly could >> >>> >> tell us something. But the best solution would probably involve querying >> >>> >> it from the audio driver. >> >>> >> >> >>> > >> >>> > The last time I checked with the audio folks, the driver does not change >> >>> > the BCLK freq. and the default is 96 MHz. >> >>> >> >>> So, what should we do for now? Block 168? Remove 168? >> >> >> >> As Ville wrote, bdw_adjust_min_pipe_pixel_rate() already does that. You >> >> just have to modify intel_max_pixel_rate() to include CNL too. >> > >> >> oh, so just squash [PATCH 67/67] drm/i915/cnl: Adjust min pixelrate. >> here? >> > > I completely forgot about that patch, makes sense to squash that here. squashed locally here... I will send out on next chunck... > > > >> > >> >> >> >> -DK >> >> >> >>> >> >>> > >> >>> > >> >>> >> > >> >>> >> > > >> >>> >> > > > + >> >>> >> > > > + if (cdclk > dev_priv->max_cdclk_freq) { >> >>> >> > > > + DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", >> >>> >> > > > + cdclk, dev_priv->max_cdclk_freq); >> >>> >> > > > + return -EINVAL; >> >>> >> > > > + } >> >>> >> > > > + >> >>> >> > > > + intel_state->cdclk.logical.vco = vco; >> >>> >> > > > + intel_state->cdclk.logical.cdclk = cdclk; >> >>> >> > > > + >> >>> >> > > > + if (!intel_state->active_crtcs) { >> >>> >> > > > + cdclk = cnl_calc_cdclk(0); >> >>> >> > > > + vco = cnl_cdclk_pll_vco(dev_priv, cdclk); >> >>> >> > > > + >> >>> >> > > > + intel_state->cdclk.actual.vco = vco; >> >>> >> > > > + intel_state->cdclk.actual.cdclk = cdclk; >> >>> >> > > > + } else { >> >>> >> > > > + intel_state->cdclk.actual = >> >>> >> > > > + intel_state->cdclk.logical; >> >>> >> > > > + } >> >>> >> > > > + >> >>> >> > > > + return 0; >> >>> >> > > > +} >> >>> >> > > > + >> >>> >> > > > static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) >> >>> >> > > > { >> >>> >> > > > int max_cdclk_freq = dev_priv->max_cdclk_freq; >> >>> >> > > > @@ -1959,7 +2003,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) >> >>> >> > > > */ >> >>> >> > > > void intel_update_max_cdclk(struct drm_i915_private *dev_priv) >> >>> >> > > > { >> >>> >> > > > - if (IS_GEN9_BC(dev_priv)) { >> >>> >> > > > + if (IS_CANNONLAKE(dev_priv)) { >> >>> >> > > > + dev_priv->max_cdclk_freq = 528000; >> >>> >> > > > + } else if (IS_GEN9_BC(dev_priv)) { >> >>> >> > > > u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; >> >>> >> > > > int max_cdclk, vco; >> >>> >> > > > >> >>> >> > > > @@ -2158,6 +2204,10 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) >> >>> >> > > > dev_priv->display.set_cdclk = skl_set_cdclk; >> >>> >> > > > dev_priv->display.modeset_calc_cdclk = >> >>> >> > > > skl_modeset_calc_cdclk; >> >>> >> > > > + } else if (IS_CANNONLAKE(dev_priv)) { >> >>> >> > > > + dev_priv->display.set_cdclk = cnl_set_cdclk; >> >>> >> > > > + dev_priv->display.modeset_calc_cdclk = >> >>> >> > > > + cnl_modeset_calc_cdclk; >> >>> >> > > > } >> >>> >> > > > >> >>> >> > > > if (IS_CANNONLAKE(dev_priv)) >> >>> >> > > > -- >> >>> >> > > > 1.9.1 >> >>> >> > > > >> >>> >> > > > _______________________________________________ >> >>> >> > > > Intel-gfx mailing list >> >>> >> > > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> >>> >> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >>> >> > >> >>> >> >> >>> > >> >>> > _______________________________________________ >> >>> > Intel-gfx mailing list >> >>> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx >> >>> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> >>> >> >>> >> >>> >> >> >> > >> > >> > >> > -- >> > Rodrigo Vivi >> > Blog: http://blog.vivi.eng.br >> >> >> > -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx