On Tue, Jun 06, 2017 at 03:43:18PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > The number of compressed segments has been available ever since > FBC2 was introduced in g4x, it just moved from the STATUS register > into STATUS2 on IVB. > > For FBC1 if we really wanted the number of compressed segments we'd > have to trawl through the tags, but in this case since the code just > uses the number of compressed segments as an indicator whether > compression has occurred we can just check the state of the > COMPRESSING and COMPRESSED bits. IIRC the hardware will try to > periodically recompress all uncompressed lines even if they haven't > changed and the COMPRESSED bit will be cleared while the compressor > is running, so just checking the COMPRESSED bit might not give us > the right answer. Hence it seems better to check for both > COMPRESSED and COMPRESSING as that should tell us that the > compressor is at least trying to do something. > > While at it move the IVB+ register define to the right place, unify > the naming convention of the compressed segment count masks, and > fix up the mask for g4x. > > v2: s/ILK_DPFC_STATUS2/IVB_FBC_STATUS2/ (Paulo) > > Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > Cc: Gabriel Krisman Bertazi <krisman@xxxxxxxxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Tested-by: Gabriel Krisman Bertazi <krisman@xxxxxxxxxxxxxxx> # SNB > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> # ilk+ > Acked-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> # pre-ilk Pushed to dinq. Thanks for the review and testing. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
