On Mon, 2017-06-05 at 18:55 +0300, Imre Deak wrote:
> On Thu, Apr 06, 2017 at 12:15:22PM -0700, Rodrigo Vivi wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > CNL power wells are very similar to SKL, with the exception that the
> > misc IO well has been split into separate AUX IO wells.
> >
> > Not sure if DMC is supposed to manage the AUX wells for us or not.
> > Let's assume so for now.
> >
> > v2: DDI A power well wants DDI A domains, not DDI B domains
> > v3: s/BIT/BIT_ULL and add proper Aux IO domains. (Rodrigo)
> > v4: Remove PW_DDI_E. Not supported on Current CNL SKUs. (Rodrigo).
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 5 ++
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 138 +++++++++++++++++++++++++++++++-
> > 2 files changed, 139 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 657036d..ac8a223 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1057,6 +1057,7 @@ enum skl_disp_power_wells {
> > SKL_DISP_PW_MISC_IO,
> > SKL_DISP_PW_DDI_A_E,
> > GLK_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> > + CNL_DISP_PW_DDI_A = SKL_DISP_PW_DDI_A_E,
> > SKL_DISP_PW_DDI_B,
> > SKL_DISP_PW_DDI_C,
> > SKL_DISP_PW_DDI_D,
> > @@ -1064,6 +1065,10 @@ enum skl_disp_power_wells {
> > GLK_DISP_PW_AUX_A = 8,
> > GLK_DISP_PW_AUX_B,
> > GLK_DISP_PW_AUX_C,
> > + CNL_DISP_PW_AUX_A = GLK_DISP_PW_AUX_A,
> > + CNL_DISP_PW_AUX_B = GLK_DISP_PW_AUX_B,
> > + CNL_DISP_PW_AUX_C = GLK_DISP_PW_AUX_C,
> > + CNL_DISP_PW_AUX_D,
> >
> > SKL_DISP_PW_1 = 14,
> > SKL_DISP_PW_2,
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index f8a375f..c67eb89 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -494,6 +494,57 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> >
> > +#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> > + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
>
> If port E isn't supported the above and
> CNL_DISPLAY_DDI_E_IO_POWER_DOMAINS could be also removed, unless you
> wanted to keep them for reference. Either way, looks ok:
I agree. I will remove on the next rebase.
>
> Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
Thanks.
>
> > + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> > + BIT_ULL(POWER_DOMAIN_VGA) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DDI_E_IO_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_A_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_B_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_C_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_AUX_D_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > + CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > + BIT_ULL(POWER_DOMAIN_MODESET) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > + BIT_ULL(POWER_DOMAIN_INIT))
> > +
> > static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> > {
> > WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
> > @@ -762,13 +813,14 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
> > }
> > break;
> > case SKL_DISP_PW_MISC_IO:
> > - case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A */
> > + case SKL_DISP_PW_DDI_A_E: /* GLK_DISP_PW_DDI_A, CNL_DISP_PW_DDI_A */
> > case SKL_DISP_PW_DDI_B:
> > case SKL_DISP_PW_DDI_C:
> > case SKL_DISP_PW_DDI_D:
> > - case GLK_DISP_PW_AUX_A:
> > - case GLK_DISP_PW_AUX_B:
> > - case GLK_DISP_PW_AUX_C:
> > + case GLK_DISP_PW_AUX_A: /* CNL_DISP_PW_AUX_A */
> > + case GLK_DISP_PW_AUX_B: /* CNL_DISP_PW_AUX_B */
> > + case GLK_DISP_PW_AUX_C: /* CNL_DISP_PW_AUX_C */
> > + case CNL_DISP_PW_AUX_D:
> > break;
> > default:
> > WARN(1, "Unknown power well %lu\n", power_well->id);
> > @@ -2275,6 +2327,82 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> > },
> > };
> >
> > +static struct i915_power_well cnl_power_wells[] = {
> > + {
> > + .name = "always-on",
> > + .always_on = 1,
> > + .domains = POWER_DOMAIN_MASK,
> > + .ops = &i9xx_always_on_power_well_ops,
> > + },
> > + {
> > + .name = "power well 1",
> > + /* Handled by the DMC firmware */
> > + .domains = 0,
> > + .ops = &skl_power_well_ops,
> > + .id = SKL_DISP_PW_1,
> > + },
> > + {
> > + .name = "AUX A",
> > + .domains = CNL_DISPLAY_AUX_A_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = CNL_DISP_PW_AUX_A,
> > + },
> > + {
> > + .name = "AUX B",
> > + .domains = CNL_DISPLAY_AUX_B_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = CNL_DISP_PW_AUX_B,
> > + },
> > + {
> > + .name = "AUX C",
> > + .domains = CNL_DISPLAY_AUX_C_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = CNL_DISP_PW_AUX_C,
> > + },
> > + {
> > + .name = "AUX D",
> > + .domains = CNL_DISPLAY_AUX_D_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = CNL_DISP_PW_AUX_D,
> > + },
> > + {
> > + .name = "DC off",
> > + .domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
> > + .ops = &gen9_dc_off_power_well_ops,
> > + .id = SKL_DISP_PW_DC_OFF,
> > + },
> > + {
> > + .name = "power well 2",
> > + .domains = CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = SKL_DISP_PW_2,
> > + },
> > + {
> > + .name = "DDI A IO power well",
> > + .domains = CNL_DISPLAY_DDI_A_IO_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = CNL_DISP_PW_DDI_A,
> > + },
> > + {
> > + .name = "DDI B IO power well",
> > + .domains = CNL_DISPLAY_DDI_B_IO_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = SKL_DISP_PW_DDI_B,
> > + },
> > + {
> > + .name = "DDI C IO power well",
> > + .domains = CNL_DISPLAY_DDI_C_IO_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = SKL_DISP_PW_DDI_C,
> > + },
> > + {
> > + .name = "DDI D IO power well",
> > + .domains = CNL_DISPLAY_DDI_D_IO_POWER_DOMAINS,
> > + .ops = &skl_power_well_ops,
> > + .id = SKL_DISP_PW_DDI_D,
> > + },
> > +};
> > +
> > static int
> > sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
> > int disable_power_well)
> > @@ -2369,6 +2497,8 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
> > set_power_wells(power_domains, bdw_power_wells);
> > } else if (IS_GEN9_BC(dev_priv)) {
> > set_power_wells(power_domains, skl_power_wells);
> > + } else if (IS_CANNONLAKE(dev_priv)) {
> > + set_power_wells(power_domains, cnl_power_wells);
> > } else if (IS_BROXTON(dev_priv)) {
> > set_power_wells(power_domains, bxt_power_wells);
> > } else if (IS_GEMINILAKE(dev_priv)) {
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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