On Thu, 01 Jun 2017, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Pass down the correct acquire context to the pipe A quirk load detect > hack during display resume. Avoids deadlocking the entire thing. Have we seen this in the wild? References? BR, Jani. > > Cc: stable@xxxxxxxxxxxxxxx > Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx> > Fixes: e2c8b8701e2d ("drm/i915: Use atomic helpers for suspend, v2.") > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 21 ++++++++++++--------- > 1 file changed, 12 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index ed41b59ee8e3..2f76a63efe8c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -120,7 +120,8 @@ static void intel_crtc_init_scalers(struct intel_crtc *crtc, > static void skylake_pfit_enable(struct intel_crtc *crtc); > static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); > static void ironlake_pfit_enable(struct intel_crtc *crtc); > -static void intel_modeset_setup_hw_state(struct drm_device *dev); > +static void intel_modeset_setup_hw_state(struct drm_device *dev, > + struct drm_modeset_acquire_ctx *ctx); > static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); > > struct intel_limit { > @@ -3461,7 +3462,7 @@ __intel_display_resume(struct drm_device *dev, > struct drm_crtc *crtc; > int i, ret; > > - intel_modeset_setup_hw_state(dev); > + intel_modeset_setup_hw_state(dev, ctx); > i915_redisable_vga(to_i915(dev)); > > if (!state) > @@ -15094,7 +15095,7 @@ int intel_modeset_init(struct drm_device *dev) > intel_setup_outputs(dev_priv); > > drm_modeset_lock_all(dev); > - intel_modeset_setup_hw_state(dev); > + intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); > drm_modeset_unlock_all(dev); > > for_each_intel_crtc(dev, crtc) { > @@ -15131,13 +15132,13 @@ int intel_modeset_init(struct drm_device *dev) > return 0; > } > > -static void intel_enable_pipe_a(struct drm_device *dev) > +static void intel_enable_pipe_a(struct drm_device *dev, > + struct drm_modeset_acquire_ctx *ctx) > { > struct intel_connector *connector; > struct drm_connector_list_iter conn_iter; > struct drm_connector *crt = NULL; > struct intel_load_detect_pipe load_detect_temp; > - struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; > int ret; > > /* We can't just switch on the pipe A, we need to set things up with a > @@ -15209,7 +15210,8 @@ static bool has_pch_trancoder(struct drm_i915_private *dev_priv, > (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); > } > > -static void intel_sanitize_crtc(struct intel_crtc *crtc) > +static void intel_sanitize_crtc(struct intel_crtc *crtc, > + struct drm_modeset_acquire_ctx *ctx) > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > @@ -15265,7 +15267,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) > * resume. Force-enable the pipe to fix this, the update_dpms > * call below we restore the pipe to the right state, but leave > * the required bits on. */ > - intel_enable_pipe_a(dev); > + intel_enable_pipe_a(dev, ctx); > } > > /* Adjust the state of the output pipe according to whether we > @@ -15568,7 +15570,8 @@ get_encoder_power_domains(struct drm_i915_private *dev_priv) > * and sanitizes it to the current state > */ > static void > -intel_modeset_setup_hw_state(struct drm_device *dev) > +intel_modeset_setup_hw_state(struct drm_device *dev, > + struct drm_modeset_acquire_ctx *ctx) > { > struct drm_i915_private *dev_priv = to_i915(dev); > enum pipe pipe; > @@ -15588,7 +15591,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev) > for_each_pipe(dev_priv, pipe) { > crtc = intel_get_crtc_for_pipe(dev_priv, pipe); > > - intel_sanitize_crtc(crtc); > + intel_sanitize_crtc(crtc, ctx); > intel_dump_pipe_config(crtc, crtc->config, > "[setup_hw_state]"); > } -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx