On Fri, May 26, 2017 at 08:45:45PM +0530, Mahesh Kumar wrote:
> This patch implements new DDB allocation algorithm as per HW team
> recommendation. This algo takecare of scenario where we allocate less DDB
> for the planes with lower relative pixel rate, but they require more DDB
> to work.
> It also takes care of enabling same watermark level for each
> plane in crtc, for efficient power saving.
>
> Changes since v1:
> - Rebase on top of Paulo's patch series
>
> Changes since v2:
> - Fix the for loop condition to enable WM
>
> Changes since v3:
> - Fix crash in cursor i-g-t reported by Maarten
> - Rebase after addressing Paulo's comments
> - Few other ULT fixes
> Changes since v4:
> - Rebase on drm-tip
> - Added separate function to enable WM levels
> Changes since v5:
> - Fix a crash identified in skl-6770HQ system
> Changes since v6:
> - Address review comments from Matt
> Changes since v7:
> - Fix failure return in skl_compute_plane_wm (Matt)
> - fix typo
> Changes since v8:
> - Always check cursor wm enable irrespective of total_data_rate
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
...
> @@ -4114,13 +4183,24 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
> total_data_rate = skl_get_total_relative_data_rate(cstate,
> plane_data_rate,
> plane_y_data_rate);
> + /*
> + * PLANE_CURSOR data rate is not included in total_data_rate.
> + * If, only cursor plane is enabled we have to enable it's WM
A couple minor typo's here. You probably don't want the comma after
"If," and the "it's" at the end of the line should be "its."
With those fixed,
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> + * levels explicitly before returning. Cursor has fixed ddb allocation,
> + * So it's ok to always check cursor WM enabling before return.
> + */
> + plane_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
> + skl_enable_plane_wm_levels(dev_priv, plane_blocks, max_level,
> + &pipe_wm->planes[PLANE_CURSOR]);
> if (total_data_rate == 0)
> return 0;
>
> start = alloc->start;
> for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> unsigned int data_rate, y_data_rate;
> - uint16_t plane_blocks, y_plane_blocks = 0;
> + uint16_t plane_blocks = 0, y_plane_blocks = 0;
> + struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> + uint16_t plane_res_b = wm->wm[max_level].plane_res_b;
>
> if (plane_id == PLANE_CURSOR)
> continue;
...
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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