When SW enables the use of 2M/1G pages, it must disable the GTT cache. Signed-off-by: Matthew Auld <matthew.auld@xxxxxxxxx> Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/intel_pm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 936eef1634c7..496b64f65eb2 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8195,10 +8195,10 @@ static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) /* * WaGttCachingOffByDefault:bdw - * GTT cache may not work with big pages, so if those - * are ever enabled GTT cache may need to be disabled. + * The GTT cache must be disabled if the system is planning to use + * 2M/1G pages. */ - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); + I915_WRITE(HSW_GTT_CACHE_EN, 0); /* WaKVMNotificationOnConfigChange:bdw */ I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) @@ -8474,10 +8474,10 @@ static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv) gen8_set_l3sqc_credits(dev_priv, 38, 2); /* - * GTT cache may not work with big pages, so if those - * are ever enabled GTT cache may need to be disabled. + * The GTT cache must be disabled if the system is planning to use + * 2M/1G pages. */ - I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); + I915_WRITE(HSW_GTT_CACHE_EN, 0); } static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) -- 2.9.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
