On Wed, 24 May 2017, Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx> wrote: > On Tue, 23 May 2017, Puthikorn Voravootivat <puthik@xxxxxxxxxxxx> wrote: >> This patch adds the following definition >> - Bit mask for EDP_PWMGEN_BIT_COUNT and min/max cap >> register which only use bit 0:4 >> - Base frequency (27 MHz) for backlight PWM frequency >> generator. >> >> Signed-off-by: Puthikorn Voravootivat <puthik@xxxxxxxxxxxx> >> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> >> --- >> include/drm/drm_dp_helper.h | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >> index c0bd0d7651a9..eaa307f6ae8c 100644 >> --- a/include/drm/drm_dp_helper.h >> +++ b/include/drm/drm_dp_helper.h >> @@ -572,10 +572,12 @@ >> #define DP_EDP_PWMGEN_BIT_COUNT 0x724 >> #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 >> #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 >> +# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) > ^^ > > Extra space crept in. Fixed that while applying to drm-intel-next-queued, thanks for the patch. Pushed via drm-intel with Dave's IRC ack to not require a backmerge for the subsequent patches. BR, Jani. > > BR, > Jani. > >> >> #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 >> >> #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 >> +# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 >> >> #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a >> #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
