Hi,
On Friday 07 April 2017 12:45 AM, Rodrigo Vivi wrote:
From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
TODO: Right now we only have 2 of the 4 WAs implemented. There's one
missing for render decompression and another for transition
watermarks. When we upstream this patch, let's check if those missing
WAs are also implemented. We may also consider not even adding the A0
WA to the upstream tree.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7ce56f1..83b80fa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3076,6 +3076,9 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv))
return true;
+ if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))
+ return true;
+
As per BSpec Memory Bandwidth related WA needed only for GEN9, WA#893
-Mahesh
return false;
}
@@ -3871,7 +3874,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
res_lines = DIV_ROUND_UP(selected_result.val,
plane_blocks_per_line.val);
- if (level >= 1 && level <= 7) {
+ if ((IS_GEN9(dev_priv) ||
+ IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0)) &&
+ level >= 1 && level <= 7) {
if (y_tiled) {
res_blocks += fixed_16_16_to_u32_round_up(y_tile_minimum);
res_lines += y_min_scanlines;
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