Hi all, This series implements ppgtt support that aliases the global gtt, i.e. ppgtt address space is not managed independantly, yet, this only enables the hw support. Do not ask why it took more than a month to beat this into shape. There are two reasons why 2-level ppgtt is actually faster than single level global gtt: a) The first ppgtt level is loaded into a special on-chip cache, eliminating the load latency for it. b) ppgtt ptes can be loaded with llc caching, see the ECOCHK register. Disabling this removes any ppgtt related speedups. Speedups range up to 10-15%, especially on ivb the raw blitter throughput increases quite a bit. Generally up to 5% for workloads resembling more random access patterns. Patches apply on top of my my-next branch, but should apply anywhere safe for a trivial conflict with the debugfs stuff. Reviews, test reports and flames highly welcome. Cheers, Daniel Daniel Vetter (8): agp/intel-gtt: export the scratch page dma address agp/intel-gtt: export the gtt pagetable iomapping drm/i915: initialization/teardown for the aliasing ppgtt drm/i915: ppgtt binding/unbinding support drm/i915: ppgtt register definitions drm/i915: ppgtt debugfs info drm/i915: per-ring fault reg drm/i915: enable ppgtt drivers/char/agp/intel-gtt.c | 11 +- drivers/gpu/drm/i915/i915_debugfs.c | 46 +++++- drivers/gpu/drm/i915/i915_dma.c | 14 ++- drivers/gpu/drm/i915/i915_drv.c | 2 + drivers/gpu/drm/i915/i915_drv.h | 27 +++ drivers/gpu/drm/i915/i915_gem.c | 48 +++++ drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 + drivers/gpu/drm/i915/i915_gem_gtt.c | 268 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_irq.c | 11 +- drivers/gpu/drm/i915/i915_reg.h | 37 ++++ include/drm/intel-gtt.h | 4 + 11 files changed, 464 insertions(+), 12 deletions(-) -- 1.7.6.3
