Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> writes: > ELK seems to very picky about the preconditions to reset. > Evidence on Eaglelake (8086:2e12 (rev 03)) shows that it does > not like if reset occurs when there is active ring. > > Ville found out that there is workaround with name > 'WaMediaResetMainRingCleanup' which suggests that we need to > cleanup rings before resetting. It is unclear what cleanup > exactly means but evidence shows that stopping the ring > does have an effect on reset reliability. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100998 This is wrong. Should be Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100942 > Suggested-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Tomi Sarvela <tomi.p.sarvela@xxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_uncore.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 7eaaf2225e1a..1d473cd1f8a4 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1427,6 +1427,26 @@ int i915_reg_read_ioctl(struct drm_device *dev, > return ret; > } > > +static void gen3_stop_rings(struct drm_i915_private *dev_priv) > +{ > + struct intel_engine_cs *engine; > + enum intel_engine_id id; > + > + for_each_engine(engine, dev_priv, id) { > + const i915_reg_t mode_r = RING_MI_MODE(engine->mmio_base); > + > + I915_WRITE_FW(mode_r, _MASKED_BIT_ENABLE(STOP_RING)); > + if (intel_wait_for_register_fw(dev_priv, > + mode_r, > + MODE_IDLE, > + MODE_IDLE, > + 1000)) { > + DRM_DEBUG("%s : timed out STOP_RING\n", > + engine->name); > + } > + } > +} > + > static bool i915_reset_complete(struct pci_dev *pdev) > { > u8 gdrst; > @@ -1472,6 +1492,12 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) > I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); > POSTING_READ(VDECCLK_GATE_D); > > + /* We stop engines, otherwise we might get failed reset and a > + * dead gpu (on elk). > + */ > + /* WaMediaResetMainRingCleanup:ctg,elk (supposedly) */ > + gen3_stop_rings(dev_priv); > + > pci_write_config_byte(pdev, I915_GDRST, > GRDOM_MEDIA | GRDOM_RESET_ENABLE); > ret = wait_for(g4x_reset_complete(pdev), 500); > -- > 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
