On Wed, 10 May 2017, clinton.a.taylor@xxxxxxxxx wrote: > From: Clint Taylor <clinton.a.taylor@xxxxxxxxx> > > The Analogix 7737 DP to HDMI converter requires reduced N and M values when > to operate correctly at HBR2. Detect this IC by its OUI value of 0x0022B9. I'm not happy, but I also see no alternative than to go this route. Thanks for the patch. I do think we need to start a common drm quirk database for this stuff though. Added one, and rebased this one on top: https://patchwork.freedesktop.org/series/24282/ Please give it a go; I don't have a DA200. BR, Jani. > > Cc: Jani Nikula <jani.nikula@xxxxxxxxx> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx> > > Signed-off-by: Clint Taylor <clinton.a.taylor@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_drv.h | 3 ++- > drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++-------- > drivers/gpu/drm/i915/intel_dp.c | 22 ++++++++++++++++++++-- > drivers/gpu/drm/i915/intel_dp_mst.c | 3 ++- > drivers/gpu/drm/i915/intel_drv.h | 1 + > 5 files changed, 39 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 74dffbe..492e47e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -563,7 +563,8 @@ struct intel_link_m_n { > > void intel_link_compute_m_n(int bpp, int nlanes, > int pixel_clock, int link_clock, > - struct intel_link_m_n *m_n); > + struct intel_link_m_n *m_n, > + bool reduce_m_n); > > /* Interface history: > * > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 7bcc604..8920a99 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6104,7 +6104,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, > pipe_config->fdi_lanes = lane; > > intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, > - link_bw, &pipe_config->fdi_m_n); > + link_bw, &pipe_config->fdi_m_n, false); > > ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); > if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { > @@ -6280,7 +6280,8 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, > } > > static void compute_m_n(unsigned int m, unsigned int n, > - uint32_t *ret_m, uint32_t *ret_n) > + uint32_t *ret_m, uint32_t *ret_n, > + bool reduce_m_n) > { > /* > * Reduce M/N as much as possible without loss in precision. Several DP > @@ -6288,9 +6289,11 @@ static void compute_m_n(unsigned int m, unsigned int n, > * values. The passed in values are more likely to have the least > * significant bits zero than M after rounding below, so do this first. > */ > - while ((m & 1) == 0 && (n & 1) == 0) { > - m >>= 1; > - n >>= 1; > + if (reduce_m_n) { > + while ((m & 1) == 0 && (n & 1) == 0) { > + m >>= 1; > + n >>= 1; > + } > } > > *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); > @@ -6301,16 +6304,19 @@ static void compute_m_n(unsigned int m, unsigned int n, > void > intel_link_compute_m_n(int bits_per_pixel, int nlanes, > int pixel_clock, int link_clock, > - struct intel_link_m_n *m_n) > + struct intel_link_m_n *m_n, > + bool reduce_m_n) > { > m_n->tu = 64; > > compute_m_n(bits_per_pixel * pixel_clock, > link_clock * nlanes * 8, > - &m_n->gmch_m, &m_n->gmch_n); > + &m_n->gmch_m, &m_n->gmch_n, > + reduce_m_n); > > compute_m_n(pixel_clock, link_clock, > - &m_n->link_m, &m_n->link_n); > + &m_n->link_m, &m_n->link_n, > + reduce_m_n); > } > > static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 4a6feb6..f4c0582 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1548,6 +1548,20 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp) > DRM_DEBUG_KMS("common rates: %s\n", str); > } > > +bool __intel_reduced_m_n(struct intel_dp *intel_dp) > +{ > + struct intel_dp_desc *desc = &intel_dp->desc; > + bool ret = false; > + > + /* Analogix 7737 needs reduced N and M at HBR2 link rates */ > + if (desc->oui[0] == 0x00 && > + desc->oui[1] == 0x22 && > + desc->oui[2] == 0xb9) > + ret = true; > + > + return ret; > +} > + > bool > __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc) > { > @@ -1568,6 +1582,8 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp) > if (!__intel_dp_read_desc(intel_dp, desc)) > return false; > > + intel_dp->reduce_m_n = __intel_reduced_m_n(intel_dp); > + > dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id)); > DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n", > drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink", > @@ -1790,7 +1806,8 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, > intel_link_compute_m_n(bpp, lane_count, > adjusted_mode->crtc_clock, > pipe_config->port_clock, > - &pipe_config->dp_m_n); > + &pipe_config->dp_m_n, > + intel_dp->reduce_m_n); > > if (intel_connector->panel.downclock_mode != NULL && > dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { > @@ -1798,7 +1815,8 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, > intel_link_compute_m_n(bpp, lane_count, > intel_connector->panel.downclock_mode->clock, > pipe_config->port_clock, > - &pipe_config->dp_m2_n2); > + &pipe_config->dp_m2_n2, > + intel_dp->reduce_m_n); > } > > /* > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c > index 68c788e..81fd8dc 100644 > --- a/drivers/gpu/drm/i915/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c > @@ -79,7 +79,8 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, > intel_link_compute_m_n(bpp, lane_count, > adjusted_mode->crtc_clock, > pipe_config->port_clock, > - &pipe_config->dp_m_n); > + &pipe_config->dp_m_n, > + intel_dp->reduce_m_n); > > pipe_config->dp_m_n.tu = slots; > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index e8de2f67..50e5077 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1057,6 +1057,7 @@ struct intel_dp { > > /* Displayport compliance testing */ > struct intel_dp_compliance compliance; > + bool reduce_m_n; > }; > > struct intel_lspcon { -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
