On Sat, 06 May 2017, Jim Bride <jim.bride@xxxxxxxxxxxxxxx> wrote:
> According to the eDP spec, when the count field in TEST_SINK_MISC
> increments then the six bytes of sink CRC information in the DPCD
> should be valid. Unfortunately, this doesn't seem to be the case
> on some panels, and as a result we get some incorrect and inconsistent
> values from the sink CRC DPCD locations at times. This problem exhibits
> itself more on faster processors (relative failure rates HSW < SKL < KBL.)
> In order to try and account for this, we try a lot harder to read the sink
> CRC until we get consistent values twice in a row before returning what we
> read and delay for a time before trying to read. We still see some
> occasional failures, but reading the sink CRC is much more reliable,
> particularly on SKL and KBL, with these changes than without.
Retrying seems like a good idea. But this patch retries up to 36 times
if the two consecutive reads don't match, which is excessive.
The sleeps should probably be a separate change. Also not happy about
the magic numbers there.
Also, there are plenty of what seem like unrelated changes. Whitespace,
debug logging, error checking, etc.
BR,
Jani.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> Signed-off-by: Jim Bride <jim.bride@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++--
> drivers/gpu/drm/i915/intel_dp.c | 57 ++++++++++++++++++++++++++++++++-----
> 2 files changed, 61 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 870c470..4902473 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2718,7 +2718,7 @@ static int i915_sink_crc(struct seq_file *m, void *data)
> struct intel_connector *connector;
> struct drm_connector_list_iter conn_iter;
> struct intel_dp *intel_dp = NULL;
> - int ret;
> + int ret, tries = 6;
> u8 crc[6];
>
> drm_modeset_lock_all(dev);
> @@ -2738,9 +2738,17 @@ static int i915_sink_crc(struct seq_file *m, void *data)
>
> intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
>
> - ret = intel_dp_sink_crc(intel_dp, crc);
> - if (ret)
> + memset(crc, 0, 6);
> + do {
> + ret = intel_dp_sink_crc(intel_dp, crc);
> + if (ret == -ETIMEDOUT)
> + usleep_range(500, 700);
> + } while ((ret == -ETIMEDOUT) && --tries);
> +
> + if (ret != 0) {
> + seq_printf(m, "000000000000\n");
> goto out;
> + }
>
> seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
> crc[0], crc[1], crc[2],
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 06b8bd4..217bc06 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3877,13 +3877,15 @@ static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
>
> do {
> intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
> -
> + usleep_range(16700, 17000);
> if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_TEST_SINK_MISC, &buf) < 0) {
> + DRM_DEBUG_KMS("Could not read TEST_SINK_MISC\n");
> ret = -EIO;
> goto out;
> }
> count = buf & DP_TEST_COUNT_MASK;
> + DRM_DEBUG_KMS("PSR count is %d\n", count);
> } while (--attempts && count);
>
> if (attempts == 0) {
> @@ -3928,6 +3930,8 @@ static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
> }
>
> intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
> + usleep_range(16700, 17000);
> + DRM_DEBUG_KMS("PSR Successfully started sink CRC\n");
> return 0;
> }
>
> @@ -3939,21 +3943,30 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
> u8 buf;
> int count, ret;
> int attempts = 6;
> + u8 old_crc[6];
> +
> + if (crc != NULL)
> + memset(crc, 0, 6);
> + else
> + return -ENOMEM;
>
> ret = intel_dp_sink_crc_start(intel_dp);
> - if (ret)
> + if (ret) {
> + DRM_DEBUG_KMS("Could not start sink crc; ret %d\n", ret);
> return ret;
> + }
>
> do {
> intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
> + usleep_range(16700, 17000);
>
> if (drm_dp_dpcd_readb(&intel_dp->aux,
> DP_TEST_SINK_MISC, &buf) < 0) {
> + DRM_DEBUG_KMS("Cound not read TEST_SINK_MISC\n");
> ret = -EIO;
> goto stop;
> }
> count = buf & DP_TEST_COUNT_MASK;
> -
> } while (--attempts && count == 0);
>
> if (attempts == 0) {
> @@ -3962,11 +3975,41 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
> goto stop;
> }
>
> - if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
> - ret = -EIO;
> - goto stop;
> - }
> + attempts = 6;
> + memset(old_crc, 0xFF, 6);
> + do {
> + intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
> + usleep_range(16500, 17000);
> + if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR,
> + crc, 6) < 0) {
> + DRM_DEBUG_KMS("Could not read sink crc\n");
> + ret = -EIO;
> + goto stop;
> + }
> +
> + if (memcmp(old_crc, crc, 6) == 0) {
> + DRM_DEBUG_KMS("PSR Active: %3s Matching crc values found:"
> + "%02x%02x%02x%02x%02x%02x\n",
> + yesno(dev_priv->psr.active),
> + crc[0], crc[1], crc[2],
> + crc[3], crc[4], crc[5]);
> + ret = 0;
> + goto stop;
> + } else {
> + DRM_DEBUG_KMS("PSR Active: %3s crc %02x%02x%02x%02x%02x%02x "
> + "doesn't match "
> + "previous %02x%02x%02x%02x%02x%02x\n",
> + yesno(dev_priv->psr.active),
> + crc[0], crc[1], crc[2],
> + crc[3], crc[4], crc[5],
> + old_crc[0], old_crc[1], old_crc[2],
> + old_crc[3], old_crc[4], old_crc[5]);
> + memcpy(old_crc, crc, 6);
> + }
> + } while (--attempts);
>
> + DRM_DEBUG_KMS("Failed to get CRC after 6 attempts.\n");
> + ret = -ETIMEDOUT;
> stop:
> intel_dp_sink_crc_stop(intel_dp);
> return ret;
--
Jani Nikula, Intel Open Source Technology Center
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