On Thu, 04 May 2017, Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote: > On Thu, May 04, 2017 at 06:26:04PM +0200, Michal Wajdeczko wrote: >> On Thu, May 04, 2017 at 04:22:15PM +0300, Jani Nikula wrote: >> > On Thu, 04 May 2017, Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx> wrote: >> > > We are using some scratch registers in MMIO based send function. >> > > Make their base and count flexible in preparation of upcoming >> > > GuC firmware/hardware changes. While around, change cmd len >> > > parameter verification from WARN_ON to GEM_BUG_ON as we don't >> > > need this all the time. >> > >> > I'm not generally fond of caching the registers like this or adding >> > _MMIO() wrapping outside of i915_reg.h. Sure, we have some of that here >> > and there, but here it's hard to see the rationale because you do this >> > in preparation for something that we you're not sharing. >> > >> >> I can't share details atm, but as commit message says, there will be a >> change in both offsets and number of scratch registers. >> >> Imho any wrapping around these values can't go to the i915_[guc_]reg.h file >> as that file shall include only raw MMIO definitions, without any extra >> logic that is based on GEN or PLATFORM or FW version. > > The guc->send.base + offset approach is reasonable; it is certainly > the tried and trusted approach. I would stick with it, but we just can't > help with any suggestions without seeing the destination. That pretty much sums it up. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
