On Wed, Apr 26, 2017 at 04:40:06PM +0300, Imre Deak wrote: > The current code looks like a typo, the specification calls for setting > bits 31:24 to 0x8C, while preserving bits 23:0. Fix things accordingly. Yeah, as we checked there were a couple of things in the low 24 bits with non-zero default values. Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > I'm not aware of the typo causing a real problem, so the fix is only for > consistency. > > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 85b9e2f5..19a7a1e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6369,8 +6369,8 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe > vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); > > reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); > - reg_val &= 0x8cffffff; > - reg_val = 0x8c000000; > + reg_val &= 0x00ffffff; > + reg_val |= 0x8c000000; > vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); > > reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); > -- > 2.5.0 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
