On Sun, Apr 23, 2017 at 06:06:16PM +0100, Chris Wilson wrote:
> +static inline unsigned int
> +intel_ring_set_tail(struct intel_ring *ring, unsigned int tail)
> +{
> + /* Whilst writes to the tail are strictly order, there is no
> + * serialisation between readers and the writers. The tail may be
> + * read by i915_gem_request_retire() just as it is being updated
> + * by execlists, as although the breadcrumb is complete, the context
> + * switch hasn't been seen.
> + */
> + assert_ring_tail_valid(ring, tail);
> + ring->tail = tail;
Could reinforce this with WRITE_ONCE(ring->tail, tail);
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
