v4 of [1], after patches 1-5 have been merged, and with Manasi's patches [2] and [3] rebased on top. BR, Jani. [1] http://mid.mail-archive.com/cover.1490712890.git.jani.nikula@xxxxxxxxx [2] http://patchwork.freedesktop.org/patch/msgid/1490651090-4263-1-git-send-email-manasi.d.navare@xxxxxxxxx [3] http://patchwork.freedesktop.org/patch/msgid/1489529511-7856-1-git-send-email-manasi.d.navare@xxxxxxxxx Jani Nikula (9): drm/i915/dp: use the sink rates array for max sink rates drm/i915/dp: cache common rates with sink rates drm/i915/dp: do not limit rate seek when not needed drm/i915/dp: don't call the link parameters sink parameters drm/i915/dp: add functions for max common link rate and lane count drm/i915/mst: use max link not sink lane count drm/i915/dp: localize link rate index variable more drm/i915/dp: use readb and writeb calls for single byte DPCD access drm/i915/dp: read sink count to a temporary variable first Manasi Navare (2): drm/i915/dp: Validate cached link rate and lane count before retraining drm/i915: Implement Link Rate fallback on Link training failure drivers/gpu/drm/i915/intel_dp.c | 236 +++++++++++++++----------- drivers/gpu/drm/i915/intel_dp_link_training.c | 22 ++- drivers/gpu/drm/i915/intel_dp_mst.c | 4 +- drivers/gpu/drm/i915/intel_drv.h | 15 +- 4 files changed, 172 insertions(+), 105 deletions(-) -- 2.1.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
