A piece of magic that prevents Baytrail from doing a timewarp. (Perhaps executing an incorrect portion of the ring?) If left to itself after a few hundred resets, the GPU will write a stale seqno causing all requests to be completed early and the GPU then appears idle. A msleep(1000) before the intel_gpu_reset, or after it is not sufficient, but a short delay of a few hundred microseconds after writing the RING_CTL is. Less than a few hundred us, or inserting a few more posting reads into the init_ring_common is not enough. To limit the impact, it appears we only need one after all RING_CTL writes and also we only want to apply it when writing nonzero values into the RING_HEAD/TAIL i.e. after reset. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98836 Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/i915_gem.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index bbc6f1c9f175..54e6d8b43c2b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4581,6 +4581,9 @@ static int __i915_gem_restart_engines(void *data) return err; } + /* Small piece of magic to stablize resets of an active GPU */ + msleep(1); + return 0; } -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
