On Tue, Mar 07, 2017 at 04:12:52PM -0800, Dhinakaran Pandiyan wrote:
> According to BSpec, "The CD clock frequency must be at least twice the
> frequency of the Azalia BCLK." and BCLK is configured to 96 MHz by
> default. This check is needed because BXT and GLK support cdclk
> frequencies less than 192 MHz.
>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index e8c1181..7b1ac1d 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1458,6 +1458,18 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> pixel_rate = max(432000, pixel_rate);
> }
>
> + /* According to BSpec, "The CD clock frequency must be at least twice
> + * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
> + * The check for GLK has to be adjusted as the platform can output
> + * two pixels per clock.
> + */
> + if (crtc_state->has_audio) {
> + if (IS_GEMINILAKE(dev_priv))
> + pixel_rate = max(2 * 2 * 96000, pixel_rate);
BTW that x2 factor for GLK looks wrong. It should be /2.
https://bugs.freedesktop.org/show_bug.cgi?id=100439
> + if (IS_BROXTON(dev_priv))
> + pixel_rate = max(2 * 96000, pixel_rate);
> + }
> +
> return pixel_rate;
> }
>
> --
> 2.7.4
>
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--
Ville Syrjälä
Intel OTC
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