Jani,
Should I just hold on to this until your patch series
gets merged so I can rebase this on top of it?
Regards
Manasi
On Mon, Mar 27, 2017 at 02:44:50PM -0700, Manasi Navare wrote:
> Currently intel_dp_check_link_status() tries to retrain the link if
> Clock recovery or Channel EQ for any of the lanes indicated by
> intel_dp->lane_count is not set. However these values cached in intel_dp
> structure can be stale if link training has failed for these values
> during previous modeset. Or these values can get stale since we have
> now re read the DPCD registers or it can be 0 in case of connected boot
> case.
>
> This patch validates these values against the common_rates and max lane
> count values.
>
> This is absolutely required incase the common_rates or max lane count
> are now different due to link fallback.
>
> v2:
> * Include the FIXME commnet inside the function (Ville Syrjala)
> * Remove the redundant parenthesis (Ville Syrjala)
>
> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 28 +++++++++++++++++++++++++---
> 1 file changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index fd96a6c..d0ab307 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -295,6 +295,27 @@ static int intel_dp_link_rate_index(struct intel_dp *intel_dp,
> return -1;
> }
>
> +static bool intel_dp_link_params_is_valid(struct intel_dp *intel_dp)
> +{
> + int common_rates[DP_MAX_SUPPORTED_RATES];
> + int link_rate_index;
> +
> + /* FIXME: we need to synchronize the current link parameters with
> + * hardware readout. Currently fast link training doesn't work
> + * on boot-up.
> + */
> + link_rate_index = intel_dp_link_rate_index(intel_dp,
> + common_rates,
> + intel_dp->link_rate);
> + if (link_rate_index < 0)
> + return false;
> + if (!intel_dp->lane_count ||
> + intel_dp->lane_count > intel_dp_max_lane_count(intel_dp))
> + return false;
> +
> + return true;
> +}
> +
> int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
> int link_rate, uint8_t lane_count)
> {
> @@ -4224,9 +4245,10 @@ intel_dp_check_link_status(struct intel_dp *intel_dp)
> if (!to_intel_crtc(intel_encoder->base.crtc)->active)
> return;
>
> - /* FIXME: we need to synchronize this sort of stuff with hardware
> - * readout. Currently fast link training doesn't work on boot-up. */
> - if (!intel_dp->lane_count)
> + /* Validate the cached values of intel_dp->link_rate and
> + * intel_dp->lane_count before attempting to retrain.
> + */
> + if (!intel_dp_link_params_is_valid(intel_dp))
> return;
>
> /* Retrain if Channel EQ or CR not ok */
> --
> 2.1.4
>
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