On Mon, Mar 27, 2017 at 01:07:58PM +0300, Mika Kuoppala wrote:
> Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
>
> > We have only 8bits of precise timestamps in which to complete our
> > upper/load reads, along with the switch between precision. This is not
> > always enough time to read the upper counter twice within the same time
> > slice, leading to hard lockups. Limit the number of times to prevent
> > an inifite loop (my fault for assuming we would have no trouble doing
> > the write + reads fast enough).
> >
>
> We get here only with kasan enabled? Or even without?
>
>
> > Fixes: 47c21d9a1a7b ("drm/i915: Extend vlv/chv residency resolution")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100377
> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index aece0ff88a5d..63ce70329e6e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -8355,6 +8355,7 @@ static u64 vlv_residency_raw(struct drm_i915_private *dev_priv,
> > const i915_reg_t reg)
> > {
> > u32 lower, upper, tmp;
> > + int loop = 2;
>
> loop could be larger, like 4 but as we very seldom
> get a less than usec error, I am fine with this too.
>
> Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
Pushed with max loops set to 2. I didn't feel the usecase merited trying
harder to be sure the read was as accurate as we could make it, beyond
the first attempt to prevent the wrap affecting the result.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
