Em Qui, 2017-03-16 às 17:38 +0530, Praveen Paneri escreveu:
> When FBC is enabled for linear, legacy Y-tiled and Yf-tiled
> surfaces on gen9, the cfb stride must be programmed by SW as
>
> cfb_stride = ceiling[(at least plane width in pixels)/
> (32 * compression limit factor)] * 8
>
> v2: Minor fix for a build error
>
> v3: Fixed subject, register name and platform check (Ville)
>
> Signed-off-by: Praveen Paneri <praveen.paneri@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 5d88c35..f4f0cb5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6506,6 +6506,9 @@ enum {
> #define GLK_CL1_PWR_DOWN (1 << 11)
> #define GLK_CL2_PWR_DOWN (1 << 12)
>
> +#define CHICKEN_MISC_4 _MMIO(0x4208c)
> +#define FBC_STRIDE_OVERRIDE (1<<13)
> +
> #define _CHICKEN_PIPESL_1_A 0x420b0
> #define _CHICKEN_PIPESL_1_B 0x420b4
> #define HSW_FBCQ_DIS (1 << 22)
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index ded2add..e7f259f 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -298,9 +298,17 @@ static bool ilk_fbc_is_active(struct
> drm_i915_private *dev_priv)
> static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
> {
> struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
> + struct intel_fbc_state_cache *cache = &dev_priv-
> >fbc.state_cache;
> u32 dpfc_ctl;
> int threshold = dev_priv->fbc.threshold;
>
Please add:
/* Display WA #0529: skl, kbl, bxt, glk. */
(and if you find the real name of the WA, please also add it)
I wanted to give this patch a try with kms_frontbuffer_tracking, but I
just couldn't find your IGT patch where Y tiling support is added to
it. I can see your patches that touch lib/igt_draw and kms_draw_crc,
but no patches testing kms_frontbuffer_tracking. Can you please send me
the patchwork link?
The corollary of the paragraph above is the question: do we maintain
the same pass rate as X tiling when we test it against Y tiling now?
My original goal was to block FBC Y tiling support until we added the
IGT stuff, but I see it was already enabled by someone even though we
didn't have the missing WA nor the IGT stuff... Oh, well....
> + if (IS_GEN9(dev_priv) &&
> + i915_gem_object_get_tiling(cache->vma->obj) !=
> I915_TILING_X) {
> + int cfb_stride = DIV_ROUND_UP(cache->plane.src_w,
> + (32 * threshold)) * 8;
> + I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE |
> cfb_stride);
> + }
> +
> dpfc_ctl = 0;
> if (IS_IVYBRIDGE(dev_priv))
> dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
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