Em Qua, 2017-02-01 às 12:14 +0530, Mahesh Kumar escreveu:
> Hi,
>
>
> On Tuesday 31 January 2017 09:26 PM, Ander Conselvan De Oliveira
> wrote:
> >
> > On Tue, 2017-01-31 at 20:27 +0530, Mahesh Kumar wrote:
> > >
> > > This patch adds IPC support for platforms. This patch enables IPC
> > > only for BXT/KBL platform as for SKL recommendation is to keep it
> > > disabled.
> > > IPC (Isochronous Priority Control) is the hardware feature, which
> > > dynamically controls the memory read priority of Display.
> > >
> > > When IPC is enabled, plane read requests are sent at high
> > > priority until
> > > filling above the transition watermark, then the requests are
> > > sent at
> > > lower priority until dropping below the level 0 watermark.
> > > The lower priority requests allow other memory clients to have
> > > better
> > > memory access. When IPC is disabled, all plane read requests are
> > > sent at
> > > high priority.
> > >
> > > Changes since V1:
> > > - Remove commandline parameter to disable ipc
> > > - Address Paulo's comments
> > > Changes since V2:
> > > - Address review comments
> > > - Set ipc_enabled flag
> > > Changes since V3:
> > > - move ipc_enabled flag assignment inside intel_ipc_enable
> > > function
> > > Changes since V4:
> > > - Re-enable IPC after suspend/resume
> > >
> > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 4 +++-
> > > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > > drivers/gpu/drm/i915/intel_display.c | 1 +
> > > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > > drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
> > > 5 files changed, 22 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index ca168b22ee26..5f3b22946971 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -1246,7 +1246,7 @@ int i915_driver_load(struct pci_dev *pdev,
> > > const struct
> > > pci_device_id *ent)
> > >
> > > intel_runtime_pm_enable(dev_priv);
> > >
> > > - dev_priv->ipc_enabled = false;
> > > + intel_enable_ipc(dev_priv);
> > >
> > > /* Everything is in place, we can now relax! */
> > > DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor
> > > %d\n",
> > > @@ -2439,6 +2439,8 @@ static int intel_runtime_resume(struct
> > > device *kdev)
> > >
> > > enable_rpm_wakeref_asserts(dev_priv);
> > >
> > > + intel_enable_ipc(dev_priv);
> > > +
> > > if (ret)
> > > DRM_ERROR("Runtime resume failed, disabling it
> > > (%d)\n", ret);
> > > else
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 72f9f36ae5ce..36e0a33f876c 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -6466,6 +6466,7 @@ enum {
> > > #define DISP_FBC_WM_DIS (1<<15)
> > > #define DISP_ARB_CTL2 _MMIO(0x45004)
> > > #define DISP_DATA_PARTITION_5_6 (1<<6)
> > > +#define DISP_IPC_ENABLE (1<<3)
> > > #define DBUF_CTL _MMIO(0x45008)
> > > #define DBUF_POWER_REQUEST (1<<31)
> > > #define DBUF_POWER_STATE (1<<30)
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 0bf8e1bfbe7e..1aa708b6f55e 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -17222,6 +17222,7 @@ void intel_display_resume(struct
> > > drm_device *dev)
> > > if (!ret)
> > > ret = __intel_display_resume(dev, state);
> > >
> > > + intel_enable_ipc(dev_priv);
> > > drm_modeset_drop_locks(&ctx);
> > > drm_modeset_acquire_fini(&ctx);
> > > mutex_unlock(&dev->mode_config.mutex);
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index 0cec0013ace0..ab7423b0a41b 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1787,6 +1787,7 @@ bool skl_ddb_allocation_overlaps(const
> > > struct
> > > skl_ddb_entry **entries,
> > > uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state
> > > *pipe_config);
> > > bool ilk_disable_lp_wm(struct drm_device *dev);
> > > int sanitize_rc6_option(struct drm_i915_private *dev_priv, int
> > > enable_rc6);
> > > +void intel_enable_ipc(struct drm_i915_private *dev_priv);
> > > static inline int intel_enable_rc6(void)
> > > {
> > > return i915.enable_rc6;
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > > b/drivers/gpu/drm/i915/intel_pm.c
> > > index 249623d45be0..16e83efa1118 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -4667,6 +4667,22 @@ void intel_update_watermarks(struct
> > > intel_crtc *crtc)
> > > dev_priv->display.update_wm(crtc);
> > > }
> > >
> > > +void intel_enable_ipc(struct drm_i915_private *dev_priv)
> > > +{
> > > + u32 val;
> > > +
> > > + dev_priv->ipc_enabled = false;
> > > + if (!(IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)))
> > > + return;
> > Do we want this enabled in Geminilake?
> >
> > Ander
> yes, we need to enable this for Gemnilake also, but we need
> "Transition
> WM" patch, before enabling it for GLK.
Why do we need transition WMs before enabling IPC on GLK but not on the
other platforms?
>
> -Mahesh
> >
> >
> > >
> > > +
> > > + val = I915_READ(DISP_ARB_CTL2);
> > > +
> > > + val |= DISP_IPC_ENABLE;
> > > +
> > > + I915_WRITE(DISP_ARB_CTL2, val);
> > > + dev_priv->ipc_enabled = true;
> > > +}
> > > +
> > > /*
> > > * Lock protecting IPS related data structures
> > > */
>
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