Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > We only need to clflush those cachelines that we have validated to be > read by the GPU. Userspace typically fills the batch length in > correctly, the exceptions tend to be explicit tests within igt. > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_cmd_parser.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c > index 21b1cd917d81..b9ce9a6881ea 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -1331,7 +1331,8 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, > } > > if (ret == 0 && needs_clflush_after) > - drm_clflush_virt_range(shadow_batch_obj->mm.mapping, batch_len); > + drm_clflush_virt_range(shadow_batch_obj->mm.mapping, > + (void *)cmd - shadow_batch_obj->mm.mapping); (void *)cmd - ptr_mask_bit(shadow_batch_obj->mm.mapping) We get away as the wb mapping being zero but for correctness. -Mika > i915_gem_object_unpin_map(shadow_batch_obj); > > return ret; > -- > 2.11.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
