On Mon, Mar 06, 2017 at 04:31:27PM +0200, Jani Nikula wrote:
> Use the prefix intel_dsi_vbt for all the DSI VBT functions. No
> functional changes.
>
> Cc: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> Cc: Hans de Goede <hdegoede@xxxxxxxxxx>
> Cc: Bob Paauwe <bob.j.paauwe@xxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Patches 1-4: Reviewed-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 24 ++++++++++++------------
> drivers/gpu/drm/i915/intel_dsi.h | 5 ++---
> drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 2 +-
> 3 files changed, 15 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index b9ba2d55e4e1..189b91478f8e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -806,38 +806,38 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
> /* Power on, try both CRC pmic gpio and VBT */
> if (intel_dsi->gpio_panel)
> gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
> intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
>
> /* Deassert reset */
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
>
> /* Put device in ready state (LP-11) */
> intel_dsi_device_ready(encoder);
>
> /* Send initialization commands in LP mode */
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
>
> /* Enable port in pre-enable phase itself because as per hw team
> * recommendation, port should be enabled befor plane & pipe */
> if (is_cmd_mode(intel_dsi)) {
> for_each_dsi_port(port, intel_dsi->ports)
> I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
> } else {
> msleep(20); /* XXX */
> for_each_dsi_port(port, intel_dsi->ports)
> dpi_send_cmd(intel_dsi, TURN_ON, false, port);
> intel_dsi_msleep(intel_dsi, 100);
>
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
>
> intel_dsi_port_enable(encoder);
> }
>
> intel_panel_enable_backlight(intel_dsi->attached_connector);
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
> }
>
> static void intel_dsi_enable_nop(struct intel_encoder *encoder,
> @@ -863,7 +863,7 @@ static void intel_dsi_pre_disable(struct intel_encoder *encoder,
>
> DRM_DEBUG_KMS("\n");
>
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
> intel_panel_disable_backlight(intel_dsi->attached_connector);
>
> /*
> @@ -925,8 +925,8 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
> * some next enable sequence send turn on packet error is observed
> */
> if (is_cmd_mode(intel_dsi))
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
>
> /* Transition to LP-00 */
> intel_dsi_clear_device_ready(encoder);
> @@ -953,11 +953,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
> }
>
> /* Assert reset */
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
>
> /* Power off, try both CRC pmic gpio and VBT */
> intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
> - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
> + intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
> if (intel_dsi->gpio_panel)
> gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 0a3f133e8888..d395f6de041c 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -131,9 +131,6 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>
> void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
>
> -void intel_dsi_exec_vbt_sequence(struct intel_dsi *intel_dsi,
> - enum mipi_seq seq_id);
> -
> bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
> int intel_compute_dsi_pll(struct intel_encoder *encoder,
> struct intel_crtc_state *config);
> @@ -147,6 +144,8 @@ void intel_dsi_reset_clocks(struct intel_encoder *encoder,
>
> bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
> int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
> +void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
> + enum mipi_seq seq_id);
> enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
>
> #endif /* _INTEL_DSI_H */
> diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> index af1783f94d23..0dce7792643a 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> @@ -415,7 +415,7 @@ static const char *sequence_name(enum mipi_seq seq_id)
> return "(unknown)";
> }
>
> -void intel_dsi_exec_vbt_sequence(struct intel_dsi *intel_dsi,
> +void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
> enum mipi_seq seq_id)
> {
> struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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