Re: [PATCH v2 08/18] drm/i915: Skip useless watermark/FIFO related work on VLV/CHV when not needed

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On Thu, Mar 02, 2017 at 07:14:58PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> 
> Check whether anything relevant has actually change when we compute new
> watermarks for each plane in the state. If the watermarks for no
> primary/sprite planes changed we don't have to recompute the FIFO split
> or reprogram the DSBARB registers. And even the cursor watermarks didn't
> change we can skip the merge+invert step between all the planes on
> the pipe as well.
> 
> v2: s/noninverted/raw/ for consistency with other platforms
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
>  drivers/gpu/drm/i915/intel_atomic.c |  1 +
>  drivers/gpu/drm/i915/intel_drv.h    |  1 +
>  drivers/gpu/drm/i915/intel_pm.c     | 73 +++++++++++++++++++++++++++++--------
>  3 files changed, 60 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index e65818e5d2ab..50fb1f76cc5f 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -99,6 +99,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
>  	crtc_state->update_wm_pre = false;
>  	crtc_state->update_wm_post = false;
>  	crtc_state->fb_changed = false;
> +	crtc_state->fifo_changed = false;
>  	crtc_state->wm.need_postvbl_update = false;
>  	crtc_state->fb_bits = 0;
>  
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 351a14c98205..04943732255e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -573,6 +573,7 @@ struct intel_crtc_state {
>  	bool disable_cxsr;
>  	bool update_wm_pre, update_wm_post; /* watermarks are updated */
>  	bool fb_changed; /* fb on any of the planes is changed */
> +	bool fifo_changed; /* FIFO split is changed */
>  
>  	/* Pipe source size (ie. panel fitter input size)
>  	 * All planes will be positioned inside this space,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f7cc013b3a78..2566c88d8c89 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
<snip>
> @@ -4630,6 +4671,8 @@ void vlv_wm_get_hw_state(struct drm_device *dev)
>  		active->num_levels = wm->level + 1;
>  		active->cxsr = wm->cxsr;
>  
> +		vlv_get_fifo_size(crtc_state);
> +

Entire series pushed to dinq. While doing that I spotted this spurious
vlv_get_fifo_size() call being added here. There's an identical call
just a few lines earlier in the code, so I just dropped this extra call
while applying the patch.

Thanks for the review.

>  		/* FIXME sanitize things more */
>  		for (level = 0; level < active->num_levels; level++) {
>  			struct vlv_pipe_wm *raw =
> -- 
> 2.10.2

-- 
Ville Syrjälä
Intel OTC
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