On Thu, Mar 02, 2017 at 11:15:29AM -0800, Rodrigo Vivi wrote:
> No functional change. Just a proper organization of the gen9 workarounds.
>
> Cc: Imre Deak <imre.deak@xxxxxxxxx>
> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxx>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 42 +++++++++++++++++-----------------
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index c4d4698..796d652 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -703,22 +703,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>
> - /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> - WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> - GEN9_DG_MIRROR_FIX_ENABLE);
> -
> - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> - WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> - GEN9_RHWO_OPTIMIZATION_DISABLE);
> - /*
> - * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> - * but we do that in per ctx batchbuffer as there is an issue
> - * with this register not getting restored on ctx restore
> - */
> - }
> -
> /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
> WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
> GEN9_ENABLE_GPGPU_PREEMPTION);
> @@ -732,11 +716,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> GEN9_CCS_TLB_PREFETCH_ENABLE);
>
> - /* WaDisableMaskBasedCammingInRCC:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> - WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> - PIXEL_MASK_CAMMING_DISABLE);
> -
> /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
> WA_SET_BIT_MASKED(HDC_CHICKEN0,
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> @@ -882,6 +861,27 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> if (ret)
> return ret;
>
> + /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
Hmm. I thought someone had already nuked all BXT pre-production
workarounds. I wonder why these still exist...
> + WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> + GEN9_DG_MIRROR_FIX_ENABLE);
> +
> + /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> + GEN9_RHWO_OPTIMIZATION_DISABLE);
> + /*
> + * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> + * but we do that in per ctx batchbuffer as there is an issue
> + * with this register not getting restored on ctx restore
> + */
> + }
> +
> + /* WaDisableMaskBasedCammingInRCC:bxt */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> + WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> + PIXEL_MASK_CAMMING_DISABLE);
> +
> /* WaStoreMultiplePTEenable:bxt */
> /* This is a requirement according to Hardware specification */
> if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> --
> 1.9.1
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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