During initialisation, we set different flags for different architectures - these should be preserved when we reload the RPS thresholds. If we use a mmio read, it will first ensure that the threshold registers are written before we apply the latch in RP_CONTROL. Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> Cc: stable@xxxxxxxxxxxxxxx --- drivers/gpu/drm/i915/intel_pm.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 096bc7a6ebde..31ee7db8e26c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4884,13 +4884,8 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) GT_INTERVAL_FROM_US(dev_priv, ei_down * threshold_down / 100)); - I915_WRITE_FW(GEN6_RP_CONTROL, - GEN6_RP_MEDIA_TURBO | - GEN6_RP_MEDIA_HW_NORMAL_MODE | - GEN6_RP_MEDIA_IS_GFX | - GEN6_RP_ENABLE | - GEN6_RP_UP_BUSY_AVG | - GEN6_RP_DOWN_IDLE_AVG); + /* Restart RPS to reload the thresholds */ + I915_WRITE_FW(GEN6_RP_CONTROL, I915_READ_FW(GEN6_RP_CONTROL)); intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); spin_unlock_irq(&dev_priv->uncore.lock); -- 2.11.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
