On Wed, Feb 15, 2017 at 04:03:33PM +0000, Chris Wilson wrote: > On Wed, Feb 15, 2017 at 01:52:12PM -0000, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [1/2] drm/i915: Use a heavyweight irq-seqno barrier for gen6+ > > URL : https://patchwork.freedesktop.org/series/19697/ > > State : failure > > > > == Summary == > > > > Series 19697v1 Series without cover letter > > https://patchwork.freedesktop.org/api/1.0/series/19697/revisions/1/mbox/ > > > > Test gem_sync: > > Subgroup basic-store-each: > > pass -> FAIL (fi-ilk-650) > > But that rules out this method as being the "ideal" delay. Back to the > drawing board. And the failure on hang tells me that the SyncFlush only occurs between CS steps (and not inside batches). As demonstrated aptly by the hanging batch, that is itself less than ideal. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
