On Fri, Aug 12, 2016 at 06:46:41PM +0530, deepak.s@xxxxxxxxxxxxxxx wrote:
> From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
>
> With latest Punit FW, vgg input voltag drop falling to minimum is fixed.
> So reverting the WA patch & moving to turbo freq opreation range to [RPn -> RP0]
>
> This is not a 1:1 revert of the commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44.
> You can refer to commit 5b5929cbe3f7 ("drm/i915/chv: remove
> pre-production hardware workarounds") as the reason for the discrepancy
>
> commit 5b7c91b78b1ce6663e0f1f037f6cb4d7c9537d44
> Author: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> Date: Sat May 9 18:15:46 2015 +0530
>
> drm/i915/chv: Set min freq to efficient frequency on chv
>
> v2: Fix inconsistent return type. (Chris)
> v3: drop pre-production hw case (Ville)
>
> Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
I was never able to reproduce the supposed Punit problems with <RPe
frequencies. In fact what I always observed was that the voltage did end
up lower at RPn than at RPe. IIRC it might have been lower even while
we were in RC6. I can't actually double check that right now since they
made SVID inaccessible via sideband on CHV and I'm too lazy to set up
the extra equipment for it now.
What I can say is that RAPL is reporting ~10 mW lower power consumption
with vsynced glxgears running when we're running at 200 MHz rather than
at 400 MHz. So I'm going to decalare this patch good.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
and pushed to dinq. Thanks for the patch.
> ---
> drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 81ab119..fa80881 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5579,6 +5579,17 @@ static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
> return rp1;
> }
>
> +static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv)
> +{
> + u32 val, rpn;
> +
> + val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE);
> + rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) &
> + FB_GFX_FREQ_FUSE_MASK);
> +
> + return rpn;
> +}
> +
> static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
> {
> u32 val, rp1;
> @@ -5818,8 +5829,7 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
> intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> dev_priv->rps.rp1_freq);
>
> - /* PUnit validated range is only [RPe, RP0] */
> - dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
> + dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> dev_priv->rps.min_freq);
> --
> 1.9.1
--
Ville Syrjälä
Intel OTC
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