On Fri, Feb 10, 2017 at 03:29:57PM +0200, Ander Conselvan de Oliveira wrote: > In Geminilake, the DDI IO power domains can't be enabled before a DPLL > is running and mapped to the appropriate DDI. At least on Geminilake, > attempting to enable those during init will lead to a timeout. > > The failure to enable the power domain also causes issues with the state > verifier during resume from suspend. After all the init power domains > are enabled, the call to intel_power_domains_sync_hw() from the resume > path will cause the hw_enabled field on the respective power wells to be > false while the usage count remains above zero. Further attempts to > enable the power domain caused by a modeset will simply update the usage > count without doing anything else. When the state verifier attempts to > read the state of a DDI encoder, intel_display_power_get_if_enabled() > returns false, leading to the following WARN: > > WARNING: CPU: 3 PID: 1743 at drivers/gpu/drm/i915/intel_display.c:7001 verify_connector_state.isra.80+0x26c/0x2b0 [i915] > attached crtc is active, but connector isn't > Modules linked in: i915(E) tun ip6t_rpfilter ip6t_REJECT nf_reject_ipv6 xt_conntrack ebtable_broute bridge stp llc ebtable_nat ip6table_mangle ip6table_security ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_raw iptable_mangle iptable_security iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack iptable_raw ebtable_filter ebtables ip6table_filter ip6_tables x86_pkg_temp_thermal coretemp kvm_intel kvm i2c_algo_bit drm_kms_helper irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel drm shpchp tpm_tis tpm_tis_core tpm nfsd auth_rpcgss nfs_acl lockd grace sunrpc crc32c_intel serio_raw [last unloaded: i915] > CPU: 3 PID: 1743 Comm: kworker/u8:22 Tainted: G W E 4.10.0-rc3ander+ #300 > Hardware name: Intel Corp. Geminilake/GLK RVP1 DDR4 (05), BIOS GELKRVPA.X64.0023.B40.1611302145 11/30/2016 > Workqueue: events_unbound async_run_entry_fn > Call Trace: > dump_stack+0x86/0xc3 > __warn+0xcb/0xf0 > warn_slowpath_fmt+0x5f/0x80 > verify_connector_state.isra.80+0x26c/0x2b0 [i915] > intel_atomic_commit_tail+0x520/0x1000 [i915] > ? remove_wait_queue+0x70/0x70 > intel_atomic_commit+0x3f8/0x520 [i915] > ? intel_runtime_pm_put+0x6e/0xa0 [i915] > drm_atomic_commit+0x4b/0x50 [drm] > __intel_display_resume+0x72/0xc0 [i915] > intel_display_resume+0x107/0x150 [i915] > i915_drm_resume+0xe0/0x180 [i915] > i915_pm_restore+0x1e/0x30 [i915] > i915_pm_resume+0xe/0x10 [i915] > pci_pm_resume+0x64/0xa0 > dpm_run_callback+0xa1/0x2a0 > ? pci_pm_thaw+0x90/0x90 > device_resume+0xe3/0x200 > async_resume+0x1d/0x50 > async_run_entry_fn+0x39/0x170 > process_one_work+0x212/0x670 > ? process_one_work+0x197/0x670 > worker_thread+0x4e/0x490 > kthread+0x101/0x140 > ? process_one_work+0x670/0x670 > ? kthread_create_on_node+0x60/0x60 > ret_from_fork+0x2a/0x40 > > Cc: David Weinehall <david.weinehall@xxxxxxxxxxxxxxx> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx> LGTM, Reviewed-by: David Weinehall <david.weinehall@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 9 +++------ > 1 file changed, 3 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 8795679..b729a39 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -469,14 +469,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv, > BIT_ULL(POWER_DOMAIN_VGA) | \ > BIT_ULL(POWER_DOMAIN_INIT)) > #define GLK_DISPLAY_DDI_A_POWER_DOMAINS ( \ > - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ > - BIT_ULL(POWER_DOMAIN_INIT)) > + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES)) > #define GLK_DISPLAY_DDI_B_POWER_DOMAINS ( \ > - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \ > - BIT_ULL(POWER_DOMAIN_INIT)) > + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES)) > #define GLK_DISPLAY_DDI_C_POWER_DOMAINS ( \ > - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \ > - BIT_ULL(POWER_DOMAIN_INIT)) > + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES)) > #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \ > BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \ > BIT_ULL(POWER_DOMAIN_AUX_A) | \ > -- > 2.9.3 > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
