On Tue, 2017-02-07 at 18:13 +0530, Madhav Chauhan wrote:
> From: Deepak M <m.deepak@xxxxxxxxx>
>
> PLL divider range for GLK is different than that of
> BXT, hence adding the GLK range check in this patch.
>
> Signed-off-by: Deepak M <m.deepak@xxxxxxxxx>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_dsi_pll.c | 20 ++++++++++++++------
> 2 files changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 80ba02a..92071d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8321,10 +8321,12 @@ enum {
> #define BXT_DSI_PLL_PVD_RATIO_SHIFT 16
> #define BXT_DSI_PLL_PVD_RATIO_MASK (3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> #define BXT_DSI_PLL_PVD_RATIO_1 (1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define BXT_DSIC_16X_BY1 (0 << 10)
> #define BXT_DSIC_16X_BY2 (1 << 10)
> #define BXT_DSIC_16X_BY3 (2 << 10)
> #define BXT_DSIC_16X_BY4 (3 << 10)
> #define BXT_DSIC_16X_MASK (3 << 10)
> +#define BXT_DSIA_16X_BY1 (0 << 8)
> #define BXT_DSIA_16X_BY2 (1 << 8)
> #define BXT_DSIA_16X_BY3 (2 << 8)
> #define BXT_DSIA_16X_BY4 (3 << 8)
> @@ -8334,6 +8336,8 @@ enum {
>
> #define BXT_DSI_PLL_RATIO_MAX 0x7D
> #define BXT_DSI_PLL_RATIO_MIN 0x22
> +#define GLK_DSI_PLL_RATIO_MAX 0x6F
> +#define GLK_DSI_PLL_RATIO_MIN 0x22
> #define BXT_DSI_PLL_RATIO_MASK 0xFF
> #define BXT_REF_CLOCK_KHZ 19200
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c
> b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 61440e5..2771c9c 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -430,9 +430,10 @@ static void bxt_dsi_program_clocks(struct drm_device
> *dev, enum port port,
> I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> }
>
> -static int bxt_compute_dsi_pll(struct intel_encoder *encoder,
> +static int gen9lp_compute_dsi_pll(struct intel_encoder *encoder,
> struct intel_crtc_state *config)
> {
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u8 dsi_ratio;
> u32 dsi_clk;
> @@ -446,11 +447,18 @@ static int bxt_compute_dsi_pll(struct intel_encoder
> *encoder,
> * round 'up' the result
> */
> dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
> - if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> - dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> +
> + if (IS_BROXTON(dev_priv) && (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> + dsi_ratio > BXT_DSI_PLL_RATIO_MAX)) {
> DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
> return -ECHRNG;
> - }
> + } else if (IS_GEMINILAKE(dev_priv) &&
> + (dsi_ratio < GLK_DSI_PLL_RATIO_MIN ||
> + dsi_ratio > GLK_DSI_PLL_RATIO_MAX)) {
> + DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
> + return -ECHRNG;
> + } else
> + DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n");
u32 ratio_min, ratio_max;
if (IS_BROXTON()) {
ratio_min = ...
ratio_max = ...
} else if (IS_GEMINILAKE()) {
ratio_min = ...
ratio_max = ...
}
if (dsi_ratio < ratio_min || dsi_ratio > ratio_max) {
...
Ander
>
> /*
> * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
> @@ -462,7 +470,7 @@ static int bxt_compute_dsi_pll(struct intel_encoder
> *encoder,
> /* As per recommendation from hardware team,
> * Prog PVD ratio =1 if dsi ratio <= 50
> */
> - if (dsi_ratio <= 50)
> + if (IS_BROXTON(dev_priv) && dsi_ratio <= 50)
> config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1;
>
> return 0;
> @@ -522,7 +530,7 @@ int intel_compute_dsi_pll(struct intel_encoder *encoder,
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> return vlv_compute_dsi_pll(encoder, config);
> else if (IS_GEN9_LP(dev_priv))
> - return bxt_compute_dsi_pll(encoder, config);
> + return gen9lp_compute_dsi_pll(encoder, config);
>
> return -ENODEV;
> }
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