From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Rename the .get_display_clock_speed() hook to .get_cdclk(). .get_cdclk() is more specific (which clock) and it's much shorter. v2: Deal with IS_GEN9_BC() v3: Deal with i945gm_get_display_clock_speed() Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Reviewed-by: Ander Conselvan de Oliveira <conselvan2@xxxxxxxxx> Link: http://patchwork.freedesktop.org/patch/msgid/20170120182205.8141-4-ville.syrjala@xxxxxxxxxxxxxxx --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_display.c | 98 +++++++++++++-------------------- drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +- 3 files changed, 41 insertions(+), 62 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 6006694bffb5..f41496405484 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -602,7 +602,7 @@ struct intel_limit; struct dpll; struct drm_i915_display_funcs { - int (*get_display_clock_speed)(struct drm_i915_private *dev_priv); + int (*get_cdclk)(struct drm_i915_private *dev_priv); int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane); int (*compute_pipe_wm)(struct intel_crtc_state *cstate); int (*compute_intermediate_wm)(struct drm_device *dev, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 07d74e8e4ce7..8f560737c309 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5873,7 +5873,7 @@ static void intel_update_max_cdclk(struct drm_i915_private *dev_priv) static void intel_update_cdclk(struct drm_i915_private *dev_priv) { - dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv); + dev_priv->cdclk_freq = dev_priv->display.get_cdclk(dev_priv); if (INTEL_GEN(dev_priv) >= 9) DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", @@ -6411,8 +6411,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) struct drm_i915_private *dev_priv = to_i915(dev); u32 val, cmd; - WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) - != dev_priv->cdclk_freq); + WARN_ON(dev_priv->display.get_cdclk(dev_priv) != dev_priv->cdclk_freq); if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ cmd = 2; @@ -6476,8 +6475,7 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) struct drm_i915_private *dev_priv = to_i915(dev); u32 val, cmd; - WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) - != dev_priv->cdclk_freq); + WARN_ON(dev_priv->display.get_cdclk(dev_priv) != dev_priv->cdclk_freq); switch (cdclk) { case 333333: @@ -7249,7 +7247,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, return 0; } -static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int skylake_get_cdclk(struct drm_i915_private *dev_priv) { u32 cdctl; @@ -7310,7 +7308,7 @@ static void bxt_de_pll_update(struct drm_i915_private *dev_priv) dev_priv->cdclk_pll.ref; } -static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int broxton_get_cdclk(struct drm_i915_private *dev_priv) { u32 divider; int div, vco; @@ -7345,7 +7343,7 @@ static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv) return DIV_ROUND_CLOSEST(vco, div); } -static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int broadwell_get_cdclk(struct drm_i915_private *dev_priv) { uint32_t lcpll = I915_READ(LCPLL_CTL); uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; @@ -7364,7 +7362,7 @@ static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv) return 675000; } -static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int haswell_get_cdclk(struct drm_i915_private *dev_priv) { uint32_t lcpll = I915_READ(LCPLL_CTL); uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; @@ -7381,23 +7379,23 @@ static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv) return 540000; } -static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int valleyview_get_cdclk(struct drm_i915_private *dev_priv) { return vlv_get_cck_clock_hpll(dev_priv, "cdclk", CCK_DISPLAY_CLOCK_CONTROL); } -static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int ilk_get_cdclk(struct drm_i915_private *dev_priv) { return 450000; } -static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i945_get_cdclk(struct drm_i915_private *dev_priv) { return 400000; } -static int i945gm_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i945gm_get_cdclk(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -7417,17 +7415,17 @@ static int i945gm_get_display_clock_speed(struct drm_i915_private *dev_priv) } } -static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i915_get_cdclk(struct drm_i915_private *dev_priv) { return 333333; } -static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i9xx_misc_get_cdclk(struct drm_i915_private *dev_priv) { return 200000; } -static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int pnv_get_cdclk(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -7452,7 +7450,7 @@ static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv) } } -static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i915gm_get_cdclk(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -7472,12 +7470,12 @@ static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv) } } -static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i865_get_cdclk(struct drm_i915_private *dev_priv) { return 266667; } -static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i85x_get_cdclk(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 hpllcc = 0; @@ -7515,7 +7513,7 @@ static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv) return 0; } -static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i830_get_cdclk(struct drm_i915_private *dev_priv) { return 133333; } @@ -7588,7 +7586,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) return vco; } -static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int gm45_get_cdclk(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = dev_priv->drm.pdev; unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); @@ -7611,7 +7609,7 @@ static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv) } } -static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int i965gm_get_cdclk(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = dev_priv->drm.pdev; static const uint8_t div_3200[] = { 16, 10, 8 }; @@ -7649,7 +7647,7 @@ static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv) return 200000; } -static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv) +static int g33_get_cdclk(struct drm_i915_private *dev_priv) { struct pci_dev *pdev = dev_priv->drm.pdev; static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; @@ -16242,61 +16240,43 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) /* Returns the core display clock speed */ if (IS_GEN9_BC(dev_priv)) - dev_priv->display.get_display_clock_speed = - skylake_get_display_clock_speed; + dev_priv->display.get_cdclk = skylake_get_cdclk; else if (IS_GEN9_LP(dev_priv)) - dev_priv->display.get_display_clock_speed = - broxton_get_display_clock_speed; + dev_priv->display.get_cdclk = broxton_get_cdclk; else if (IS_BROADWELL(dev_priv)) - dev_priv->display.get_display_clock_speed = - broadwell_get_display_clock_speed; + dev_priv->display.get_cdclk = broadwell_get_cdclk; else if (IS_HASWELL(dev_priv)) - dev_priv->display.get_display_clock_speed = - haswell_get_display_clock_speed; + dev_priv->display.get_cdclk = haswell_get_cdclk; else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - dev_priv->display.get_display_clock_speed = - valleyview_get_display_clock_speed; + dev_priv->display.get_cdclk = valleyview_get_cdclk; else if (IS_GEN5(dev_priv)) - dev_priv->display.get_display_clock_speed = - ilk_get_display_clock_speed; + dev_priv->display.get_cdclk = ilk_get_cdclk; else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) || IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) - dev_priv->display.get_display_clock_speed = - i945_get_display_clock_speed; + dev_priv->display.get_cdclk = i945_get_cdclk; else if (IS_GM45(dev_priv)) - dev_priv->display.get_display_clock_speed = - gm45_get_display_clock_speed; + dev_priv->display.get_cdclk = gm45_get_cdclk; else if (IS_I965GM(dev_priv)) - dev_priv->display.get_display_clock_speed = - i965gm_get_display_clock_speed; + dev_priv->display.get_cdclk = i965gm_get_cdclk; else if (IS_PINEVIEW(dev_priv)) - dev_priv->display.get_display_clock_speed = - pnv_get_display_clock_speed; + dev_priv->display.get_cdclk = pnv_get_cdclk; else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) - dev_priv->display.get_display_clock_speed = - g33_get_display_clock_speed; + dev_priv->display.get_cdclk = g33_get_cdclk; else if (IS_I915G(dev_priv)) - dev_priv->display.get_display_clock_speed = - i915_get_display_clock_speed; + dev_priv->display.get_cdclk = i915_get_cdclk; else if (IS_I845G(dev_priv)) - dev_priv->display.get_display_clock_speed = - i9xx_misc_get_display_clock_speed; + dev_priv->display.get_cdclk = i9xx_misc_get_cdclk; else if (IS_I945GM(dev_priv)) - dev_priv->display.get_display_clock_speed = - i945gm_get_display_clock_speed; + dev_priv->display.get_cdclk = i945gm_get_cdclk; else if (IS_I915GM(dev_priv)) - dev_priv->display.get_display_clock_speed = - i915gm_get_display_clock_speed; + dev_priv->display.get_cdclk = i915gm_get_cdclk; else if (IS_I865G(dev_priv)) - dev_priv->display.get_display_clock_speed = - i865_get_display_clock_speed; + dev_priv->display.get_cdclk = i865_get_cdclk; else if (IS_I85X(dev_priv)) - dev_priv->display.get_display_clock_speed = - i85x_get_display_clock_speed; + dev_priv->display.get_cdclk = i85x_get_cdclk; else { /* 830 */ WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); - dev_priv->display.get_display_clock_speed = - i830_get_display_clock_speed; + dev_priv->display.get_cdclk = i830_get_cdclk; } if (IS_GEN5(dev_priv)) { diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 66aa1bbb42f0..30207353c200 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -966,8 +966,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, { gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - WARN_ON(dev_priv->cdclk_freq != - dev_priv->display.get_display_clock_speed(dev_priv)); + WARN_ON(dev_priv->cdclk_freq != dev_priv->display.get_cdclk(dev_priv)); gen9_assert_dbuf_enabled(dev_priv); -- 2.10.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
