On Tue, Feb 07, 2017 at 03:51:41PM +0200, Joonas Lahtinen wrote: > "BIT(max) - 1" will overflow when max = 32, and GCC will complain. > We already have GENMASK for generating the mask, use it! > > Signed-off-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > drivers/gpu/drm/i915/intel_fbdev.c | 2 +- > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index fcf8181..1c06fbb 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -234,7 +234,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) > * The subslice disable field is global, i.e. it applies > * to each of the enabled slices. > */ > - sseu->subslice_mask = BIT(ss_max) - 1; > + sseu->subslice_mask = GENMASK(ss_max, 0); Too simple! BUILD_BUG_ON(BIT(ss_max)-1 != GENMASK(ss_max, 0)); Needs to be GENMASK(ss_max - 1, 0); the high bit is inclusive. Otherwise, the list matches up with a quick grep for BIT*(x)-1. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
