Aliasing PPGTT mode is broken due to recent changes. Mostly boot the
system with i915.enable_ppgtt=1 will lead a kernel crash.
This patch fixes this problem by:
- PPGTT page table will not be shrinkable if working under aliasing
PPGTT mode.
- Load the root pointers of the PPGTT page table during the context
initialization, as currently the "LRI PDPs updating" magic only works
under full PPGTT mode and also GVT-g doesn't support LRI PDP updating.
Tested on my SKL NUC box.
Cc: Tvrtko Ursulin <tvrtko.ursulin@xxxxxxxxxxxxxxx>
Cc: Michal Winiarski <michal.winiarski@xxxxxxxxx>
Cc: Michel Thierry <michel.thierry@xxxxxxxxx>
Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Zhenyu Wang <zhenyuw@xxxxxxxxxxxxxxx>
Cc: Zhiyuan Lv <zhiyuan.lv@xxxxxxxxx>
Signed-off-by: Zhi Wang <zhi.a.wang@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 ++++++++++++---
drivers/gpu/drm/i915/intel_lrc.c | 5 +++++
2 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 68ecfc1..4e06056 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -754,10 +754,19 @@ static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
GEM_BUG_ON(pte_end > GEN8_PTES);
- bitmap_clear(pt->used_ptes, pte, num_entries);
+ /*
+ * As there is only one PPGTT page table used to mirror the GGTT
+ * space in the system under aliasing PPGTT mode, we don't need
+ * to shrink it. Leave the PT pages "always used", so the upper
+ * level page table pages are safe during clear_range().
+ *
+ */
+ if (USES_FULL_PPGTT(vm->i915)) {
+ bitmap_clear(pt->used_ptes, pte, num_entries);
- if (bitmap_empty(pt->used_ptes, GEN8_PTES))
- return true;
+ if (bitmap_empty(pt->used_ptes, GEN8_PTES))
+ return true;
+ }
pt_vaddr = kmap_px(pt);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 44a92ea..9575562 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2009,6 +2009,11 @@ static void execlists_init_reg_state(u32 *reg_state,
* other PDP Descriptors are ignored.
*/
ASSIGN_CTX_PML4(ppgtt, reg_state);
+ } else {
+ ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
+ ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
+ ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
+ ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
}
if (engine->id == RCS) {
--
1.9.1
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