On Thu, 02 Feb 2017, "Pandiyan, Dhinakaran" <dhinakaran.pandiyan@xxxxxxxxx> wrote: > On Thu, 2017-01-26 at 21:44 +0200, Jani Nikula wrote: >> Now that source rates are static and sink rates are updated whenever >> DPCD is updated, we can do and cache the intersection of them whenever >> sink rates are updated. This reduces code complexity, as we don't have >> to keep calling the functions to intersect. We also get rid of several >> common rates arrays on stack. >> >> Limiting the common rates by a max link rate can be done by picking the >> first N elements of the cached common rates. >> >> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx> >> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> >> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx> >> --- >> drivers/gpu/drm/i915/intel_dp.c | 66 ++++++++++++++++++++++------------------ >> drivers/gpu/drm/i915/intel_drv.h | 3 ++ >> 2 files changed, 40 insertions(+), 29 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c >> index f163391e61fa..7d3ff92000c3 100644 >> --- a/drivers/gpu/drm/i915/intel_dp.c >> +++ b/drivers/gpu/drm/i915/intel_dp.c >> @@ -283,17 +283,29 @@ static int intel_dp_find_rate(const int *rates, int len, int rate) >> return -1; >> } >> >> -static int intel_dp_common_rates(struct intel_dp *intel_dp, >> - int *common_rates) >> +static void intel_dp_set_common_rates(struct intel_dp *intel_dp) >> { >> - int max_rate = intel_dp->max_sink_link_rate; >> - int i, common_len; >> + WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); >> >> - common_len = intersect_rates(intel_dp->source_rates, >> - intel_dp->num_source_rates, >> - intel_dp->sink_rates, >> - intel_dp->num_sink_rates, >> - common_rates); >> + intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, >> + intel_dp->num_source_rates, >> + intel_dp->sink_rates, >> + intel_dp->num_sink_rates, >> + intel_dp->common_rates); > > > Do we need to pass all these args given that all of them are now > available in intel_dp and intersect_rates() is not used anywhere else? My reasoning is that with this interface intersect_rates remains generic, independent of intel_dp or anything else, and you can be sure it's stateless. BR, Jani. > > -DK >> + >> + /* Paranoia, there should always be something in common. */ >> + if (WARN_ON(intel_dp->num_common_rates == 0)) { >> + intel_dp->common_rates[0] = default_rates[0]; >> + intel_dp->num_common_rates = 1; >> + } >> +} >> + >> +/* get length of common rates potentially limited by max_rate */ >> +static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp, >> + int max_rate) >> +{ >> + const int *common_rates = intel_dp->common_rates; >> + int i, common_len = intel_dp->num_common_rates; >> >> /* Limit results by potentially reduced max rate */ >> for (i = 0; i < common_len; i++) { >> @@ -304,25 +316,23 @@ static int intel_dp_common_rates(struct intel_dp *intel_dp, >> return 0; >> } >> >> -static int intel_dp_link_rate_index(struct intel_dp *intel_dp, >> - int *common_rates, int link_rate) >> +static int intel_dp_link_rate_index(struct intel_dp *intel_dp, int link_rate) >> { >> int common_len; >> >> - common_len = intel_dp_common_rates(intel_dp, common_rates); >> + common_len = intel_dp_common_len_rate_limit(intel_dp, >> + intel_dp->max_sink_link_rate); >> >> - return intel_dp_find_rate(common_rates, common_len, link_rate); >> + return intel_dp_find_rate(intel_dp->common_rates, common_len, link_rate); >> } >> >> int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, >> int link_rate, uint8_t lane_count) >> { >> - int common_rates[DP_MAX_SUPPORTED_RATES]; >> + const int *common_rates = intel_dp->common_rates; >> int link_rate_index; >> >> - link_rate_index = intel_dp_link_rate_index(intel_dp, >> - common_rates, >> - link_rate); >> + link_rate_index = intel_dp_link_rate_index(intel_dp, link_rate); >> if (link_rate_index > 0) { >> intel_dp->max_sink_link_rate = common_rates[link_rate_index - 1]; >> intel_dp->max_sink_lane_count = lane_count; >> @@ -1509,8 +1519,6 @@ static void snprintf_int_array(char *str, size_t len, >> >> static void intel_dp_print_rates(struct intel_dp *intel_dp) >> { >> - int common_len; >> - int common_rates[DP_MAX_SUPPORTED_RATES]; >> char str[128]; /* FIXME: too big for stack? */ >> >> if ((drm_debug & DRM_UT_KMS) == 0) >> @@ -1524,8 +1532,8 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp) >> intel_dp->sink_rates, intel_dp->num_sink_rates); >> DRM_DEBUG_KMS("sink rates: %s\n", str); >> >> - common_len = intel_dp_common_rates(intel_dp, common_rates); >> - snprintf_int_array(str, sizeof(str), common_rates, common_len); >> + snprintf_int_array(str, sizeof(str), >> + intel_dp->common_rates, intel_dp->num_common_rates); >> DRM_DEBUG_KMS("common rates: %s\n", str); >> } >> >> @@ -1563,14 +1571,14 @@ bool intel_dp_read_desc(struct intel_dp *intel_dp) >> int >> intel_dp_max_link_rate(struct intel_dp *intel_dp) >> { >> - int rates[DP_MAX_SUPPORTED_RATES] = {}; >> int len; >> >> - len = intel_dp_common_rates(intel_dp, rates); >> + len = intel_dp_common_len_rate_limit(intel_dp, >> + intel_dp->max_sink_link_rate); >> if (WARN_ON(len <= 0)) >> return 162000; >> >> - return rates[len - 1]; >> + return intel_dp->common_rates[len - 1]; >> } >> >> int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) >> @@ -1639,11 +1647,12 @@ intel_dp_compute_config(struct intel_encoder *encoder, >> int link_rate_index; >> int bpp, mode_rate; >> int link_avail, link_clock; >> - int common_rates[DP_MAX_SUPPORTED_RATES] = {}; >> + const int *common_rates = intel_dp->common_rates; >> int common_len; >> uint8_t link_bw, rate_select; >> >> - common_len = intel_dp_common_rates(intel_dp, common_rates); >> + common_len = intel_dp_common_len_rate_limit(intel_dp, >> + intel_dp->max_sink_link_rate); >> >> /* No common link rates between source and sink */ >> WARN_ON(common_len <= 0); >> @@ -1681,7 +1690,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, >> /* Use values requested by Compliance Test Request */ >> if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { >> link_rate_index = intel_dp_link_rate_index(intel_dp, >> - common_rates, >> intel_dp->compliance.test_link_rate); >> if (link_rate_index >= 0) >> min_clock = max_clock = link_rate_index; >> @@ -3724,6 +3732,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) >> } else { >> intel_dp_set_sink_rates(intel_dp); >> } >> + intel_dp_set_common_rates(intel_dp); >> >> return true; >> } >> @@ -3736,6 +3745,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) >> return false; >> >> intel_dp_set_sink_rates(intel_dp); >> + intel_dp_set_common_rates(intel_dp); >> >> if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, >> &intel_dp->sink_count, 1) < 0) >> @@ -3958,7 +3968,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) >> { >> int status = 0; >> int min_lane_count = 1; >> - int common_rates[DP_MAX_SUPPORTED_RATES] = {}; >> int link_rate_index, test_link_rate; >> uint8_t test_lane_count, test_link_bw; >> /* (DP CTS 1.2) >> @@ -3987,7 +3996,6 @@ static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) >> /* Validate the requested link rate */ >> test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); >> link_rate_index = intel_dp_link_rate_index(intel_dp, >> - common_rates, >> test_link_rate); >> if (link_rate_index < 0) >> return DP_TEST_NAK; >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h >> index ae7259eda420..3578a7dd584a 100644 >> --- a/drivers/gpu/drm/i915/intel_drv.h >> +++ b/drivers/gpu/drm/i915/intel_drv.h >> @@ -936,6 +936,9 @@ struct intel_dp { >> /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */ >> int num_sink_rates; >> int sink_rates[DP_MAX_SUPPORTED_RATES]; >> + /* intersection of source and sink rates */ >> + int num_common_rates; >> + int common_rates[DP_MAX_SUPPORTED_RATES]; >> /* Max lane count for the sink as per DPCD registers */ >> uint8_t max_sink_lane_count; >> /* Max link BW for the sink as per DPCD registers */ > -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx