> -----Original Message----- > From: Chauhan, Madhav > Sent: Monday, January 2, 2017 6:24 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Nikula, Jani <jani.nikula@xxxxxxxxx>; Shankar, Uma > <uma.shankar@xxxxxxxxx>; Mukherjee, Indranil > <indranil.mukherjee@xxxxxxxxx>; Kamath, Sunil <sunil.kamath@xxxxxxxxx>; > Saarinen, Jani <jani.saarinen@xxxxxxxxx>; Conselvan De Oliveira, Ander > <ander.conselvan.de.oliveira@xxxxxxxxx>; Konduru, Chandra > <chandra.konduru@xxxxxxxxx>; Kumar, Shobhit > <shobhit.kumar@xxxxxxxxx>; Syrjala, Ville <ville.syrjala@xxxxxxxxx>; > Chauhan, Madhav <madhav.chauhan@xxxxxxxxx> > Subject: [GLK MIPI DSI V3 0/7] GLK MIPI DSI VIDEO MODE PATCHES > > The patches in this list enable MIPI DSI video mode support for GLK platform. > Tesed locally. > v2: Renamed bitfields macros as per review comments(Jani) > v3: Code alignment/abstraction as per arch (Jani review comments) > Found one issue in the MIPI DSI disable sequence during the testing. Working on fix. Will be able to publish the next series having fix and Jani review comments for couple of patches. > Deepak M (7): > drm/i915/glk: Program dphy param reg for GLK > drm/i915/glk: Program new MIPI DSI PHY registers for GLK > drm/i915/glk: Add MIPIIO Enable/disable sequence > drm/i915: Set the Z inversion overlap field > drm/i915/glk: Add DSI PLL divider range for glk > drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT > drm/i915/glk: Program txesc clock divider for GLK > > drivers/gpu/drm/i915/i915_reg.h | 17 +++ > drivers/gpu/drm/i915/intel_dsi.c | 207 > ++++++++++++++++++++++++++++- > drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 33 ++++- > drivers/gpu/drm/i915/intel_dsi_pll.c | 106 ++++++++++++--- > 4 files changed, 332 insertions(+), 31 deletions(-) > > -- > 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
