Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> writes: >> >> > Now if someone could figure out where to dig up the DDR and FSB clocks >> > we could also fix up the 190 vs. 200 MHz case... >> > >> >> + default: >> >> + case GC_DISPLAY_CLOCK_190_200_MHZ: >> >> + return 200000; >> >> + } >> >> + } >> >> +} >> >> + >> >> Hmm that seems to be 915gm specific (always 200 on 945gm). According to >> "Mobile Intel® 915/910 Express Chipset: Datasheet", the only fsb/dram >> combo that has 190MHz is FSB: 533MHz, DDR333. All the other supported >> combos have 200Mhz set by that configuration. > > Yeah. Unfortunately I couldn't find a solid source of FSB/DDR clock > information in the spec, apart from the actual strap pins but I can't > see any register that would reflect those. So I guess we'll just leave > it the way it is. Hmm "Mobile Intel® 915GM/PM/GME/GMS and 910GML/GMLE Express Chipset Specification Update" seems to sketch an even more complicated scenario, where it even depends on the GMCH subtype... FSB and also DRAM freq can be probably be fetched from respectively [2:0] and [6:4] of CLKCFG, MCHBAR(0xC00) but not documented. On 945GM I think the voltage strap is on DFT_STRAP1 bit20, MCHBAR(0xE08) (also not really documented but this is how it is done in Coreboot). It might be the same on 915GM... Given that getting the 915GM display clock correctly probably ends up being quite different from 945GM it might make sense to have 2 separate functions for that? Kind regards -- Arthur Heymans _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
