On Fri, Jan 27, 2017 at 08:55:19AM -0600, Pierre-Louis Bossart wrote: > > > >>>>> +#define AUD_PORT_EN_B_DBG 0x62F20 > >>>>> +#define AUD_PORT_EN_C_DBG 0x62F28 > >>>>> +#define AUD_PORT_EN_D_DBG 0x62F2C > >>> These match the spec. But to match the standard i915 convention they > >>> should be called _AUD_PORT_EN_B_DBG etc. Same forthe chicken bit > >>> register. > >> Actually they just match one version of the spec I had lying around. > >> Another versions says: > >> > >> AUD_PORT_EN_B_DBG 0x62F20 > >> AUD_PORT_EN_C_DBG 0x62F30 > >> AUD_PORT_EN_D_DBG 0x62F34 > > That's it! Now finally I can hear the audio from DP3 with the > > additional patch below. > Wow. Thanks Ville for looking into this, we could have lost a lot of > time. Do you happen to know if those previous values are due to poor > documentation or a different skew we'd need to support, e.g. with a > PCI-Id quirk? No idea really. You should really test this on both CHV and VLV with all possible port/pipe combinations to make sure we got it right. I trust these VLV/CHV docs about as much as I trust most politicians. Alternatively you could just read all those regs on both platforms and see if the values you get from them conform to any visible pattern that could tell us which offsets are the correct ones. They might not, in which case actual testing is the best bet. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
